Line data Source code
1 : // SPDX-License-Identifier: GPL-2.0+
2 : /* Synopsys DesignWare 8250 library. */
3 :
4 : #include <linux/bitops.h>
5 : #include <linux/bitfield.h>
6 : #include <linux/delay.h>
7 : #include <linux/device.h>
8 : #include <linux/kernel.h>
9 : #include <linux/math.h>
10 : #include <linux/property.h>
11 : #include <linux/serial_8250.h>
12 : #include <linux/serial_core.h>
13 :
14 : #include "8250_dwlib.h"
15 :
16 : /* Offsets for the DesignWare specific registers */
17 : #define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */
18 : #define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */
19 : #define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */
20 : #define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */
21 : #define DW_UART_RAR 0xc4 /* Receive Address Register */
22 : #define DW_UART_TAR 0xc8 /* Transmit Address Register */
23 : #define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */
24 : #define DW_UART_CPR 0xf4 /* Component Parameter Register */
25 : #define DW_UART_UCV 0xf8 /* UART Component Version */
26 :
27 : /* Receive / Transmit Address Register bits */
28 : #define DW_UART_ADDR_MASK GENMASK(7, 0)
29 :
30 : /* Line Status Register bits */
31 : #define DW_UART_LSR_ADDR_RCVD BIT(8)
32 :
33 : /* Transceiver Control Register bits */
34 : #define DW_UART_TCR_RS485_EN BIT(0)
35 : #define DW_UART_TCR_RE_POL BIT(1)
36 : #define DW_UART_TCR_DE_POL BIT(2)
37 : #define DW_UART_TCR_XFER_MODE GENMASK(4, 3)
38 : #define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0)
39 : #define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1)
40 : #define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2)
41 :
42 : /* Line Extended Control Register bits */
43 : #define DW_UART_LCR_EXT_DLS_E BIT(0)
44 : #define DW_UART_LCR_EXT_ADDR_MATCH BIT(1)
45 : #define DW_UART_LCR_EXT_SEND_ADDR BIT(2)
46 : #define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3)
47 :
48 : /* Component Parameter Register bits */
49 : #define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0)
50 : #define DW_UART_CPR_AFCE_MODE BIT(4)
51 : #define DW_UART_CPR_THRE_MODE BIT(5)
52 : #define DW_UART_CPR_SIR_MODE BIT(6)
53 : #define DW_UART_CPR_SIR_LP_MODE BIT(7)
54 : #define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8)
55 : #define DW_UART_CPR_FIFO_ACCESS BIT(9)
56 : #define DW_UART_CPR_FIFO_STAT BIT(10)
57 : #define DW_UART_CPR_SHADOW BIT(11)
58 : #define DW_UART_CPR_ENCODED_PARMS BIT(12)
59 : #define DW_UART_CPR_DMA_EXTRA BIT(13)
60 : #define DW_UART_CPR_FIFO_MODE GENMASK(23, 16)
61 :
62 : /* Helper for FIFO size calculation */
63 : #define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16)
64 :
65 : /*
66 : * divisor = div(I) + div(F)
67 : * "I" means integer, "F" means fractional
68 : * quot = div(I) = clk / (16 * baud)
69 : * frac = div(F) * 2^dlf_size
70 : *
71 : * let rem = clk % (16 * baud)
72 : * we have: div(F) * (16 * baud) = rem
73 : * so frac = 2^dlf_size * rem / (16 * baud) = (rem << dlf_size) / (16 * baud)
74 : */
75 0 : static unsigned int dw8250_get_divisor(struct uart_port *p, unsigned int baud,
76 : unsigned int *frac)
77 : {
78 0 : unsigned int quot, rem, base_baud = baud * 16;
79 0 : struct dw8250_port_data *d = p->private_data;
80 :
81 0 : quot = p->uartclk / base_baud;
82 0 : rem = p->uartclk % base_baud;
83 0 : *frac = DIV_ROUND_CLOSEST(rem << d->dlf_size, base_baud);
84 :
85 0 : return quot;
86 0 : }
87 :
88 0 : static void dw8250_set_divisor(struct uart_port *p, unsigned int baud,
89 : unsigned int quot, unsigned int quot_frac)
90 : {
91 0 : dw8250_writel_ext(p, DW_UART_DLF, quot_frac);
92 0 : serial8250_do_set_divisor(p, baud, quot);
93 0 : }
94 :
95 0 : void dw8250_do_set_termios(struct uart_port *p, struct ktermios *termios,
96 : const struct ktermios *old)
97 : {
98 0 : p->status &= ~UPSTAT_AUTOCTS;
99 0 : if (termios->c_cflag & CRTSCTS)
100 0 : p->status |= UPSTAT_AUTOCTS;
101 :
102 0 : serial8250_do_set_termios(p, termios, old);
103 :
104 : /* Filter addresses which have 9th bit set */
105 0 : p->ignore_status_mask |= DW_UART_LSR_ADDR_RCVD;
106 0 : p->read_status_mask |= DW_UART_LSR_ADDR_RCVD;
107 0 : }
108 : EXPORT_SYMBOL_GPL(dw8250_do_set_termios);
109 :
110 : /*
111 : * Wait until re is de-asserted for sure. An ongoing receive will keep
112 : * re asserted until end of frame. Without BUSY indication available,
113 : * only available course of action is to wait for the time it takes to
114 : * receive one frame (there might nothing to receive but w/o BUSY the
115 : * driver cannot know).
116 : */
117 0 : static void dw8250_wait_re_deassert(struct uart_port *p)
118 : {
119 0 : ndelay(p->frame_time);
120 0 : }
121 :
122 0 : static void dw8250_update_rar(struct uart_port *p, u32 addr)
123 : {
124 0 : u32 re_en = dw8250_readl_ext(p, DW_UART_RE_EN);
125 :
126 : /*
127 : * RAR shouldn't be changed while receiving. Thus, de-assert RE_EN
128 : * if asserted and wait.
129 : */
130 0 : if (re_en)
131 0 : dw8250_writel_ext(p, DW_UART_RE_EN, 0);
132 0 : dw8250_wait_re_deassert(p);
133 0 : dw8250_writel_ext(p, DW_UART_RAR, addr);
134 0 : if (re_en)
135 0 : dw8250_writel_ext(p, DW_UART_RE_EN, re_en);
136 0 : }
137 :
138 0 : static void dw8250_rs485_set_addr(struct uart_port *p, struct serial_rs485 *rs485,
139 : struct ktermios *termios)
140 : {
141 0 : u32 lcr = dw8250_readl_ext(p, DW_UART_LCR_EXT);
142 :
143 0 : if (rs485->flags & SER_RS485_ADDRB) {
144 0 : lcr |= DW_UART_LCR_EXT_DLS_E;
145 0 : if (termios)
146 0 : termios->c_cflag |= ADDRB;
147 :
148 0 : if (rs485->flags & SER_RS485_ADDR_RECV) {
149 0 : u32 delta = p->rs485.flags ^ rs485->flags;
150 :
151 : /*
152 : * rs485 (param) is equal to uart_port's rs485 only during init
153 : * (during init, delta is not yet applicable).
154 : */
155 0 : if (unlikely(&p->rs485 == rs485))
156 0 : delta = rs485->flags;
157 :
158 0 : if ((delta & SER_RS485_ADDR_RECV) ||
159 0 : (p->rs485.addr_recv != rs485->addr_recv))
160 0 : dw8250_update_rar(p, rs485->addr_recv);
161 0 : lcr |= DW_UART_LCR_EXT_ADDR_MATCH;
162 0 : } else {
163 0 : lcr &= ~DW_UART_LCR_EXT_ADDR_MATCH;
164 : }
165 0 : if (rs485->flags & SER_RS485_ADDR_DEST) {
166 : /*
167 : * Don't skip writes here as another endpoint could
168 : * have changed communication line's destination
169 : * address in between.
170 : */
171 0 : dw8250_writel_ext(p, DW_UART_TAR, rs485->addr_dest);
172 0 : lcr |= DW_UART_LCR_EXT_SEND_ADDR;
173 0 : }
174 0 : } else {
175 0 : lcr = 0;
176 : }
177 0 : dw8250_writel_ext(p, DW_UART_LCR_EXT, lcr);
178 0 : }
179 :
180 0 : static int dw8250_rs485_config(struct uart_port *p, struct ktermios *termios,
181 : struct serial_rs485 *rs485)
182 : {
183 0 : u32 tcr;
184 :
185 0 : tcr = dw8250_readl_ext(p, DW_UART_TCR);
186 0 : tcr &= ~DW_UART_TCR_XFER_MODE;
187 :
188 0 : if (rs485->flags & SER_RS485_ENABLED) {
189 0 : tcr |= DW_UART_TCR_RS485_EN;
190 :
191 0 : if (rs485->flags & SER_RS485_RX_DURING_TX)
192 0 : tcr |= DW_UART_TCR_XFER_MODE_DE_DURING_RE;
193 : else
194 0 : tcr |= DW_UART_TCR_XFER_MODE_DE_OR_RE;
195 0 : dw8250_writel_ext(p, DW_UART_DE_EN, 1);
196 0 : dw8250_writel_ext(p, DW_UART_RE_EN, 1);
197 0 : } else {
198 0 : if (termios)
199 0 : termios->c_cflag &= ~ADDRB;
200 :
201 0 : tcr &= ~DW_UART_TCR_RS485_EN;
202 : }
203 :
204 : /* Reset to default polarity */
205 0 : tcr |= DW_UART_TCR_DE_POL;
206 0 : tcr &= ~DW_UART_TCR_RE_POL;
207 :
208 0 : if (!(rs485->flags & SER_RS485_RTS_ON_SEND))
209 0 : tcr &= ~DW_UART_TCR_DE_POL;
210 0 : if (device_property_read_bool(p->dev, "rs485-rx-active-high"))
211 0 : tcr |= DW_UART_TCR_RE_POL;
212 :
213 0 : dw8250_writel_ext(p, DW_UART_TCR, tcr);
214 :
215 : /* Addressing mode can only be set up after TCR */
216 0 : if (rs485->flags & SER_RS485_ENABLED)
217 0 : dw8250_rs485_set_addr(p, rs485, termios);
218 :
219 0 : return 0;
220 0 : }
221 :
222 : /*
223 : * Tests if RE_EN register can have non-zero value to see if RS-485 HW support
224 : * is present.
225 : */
226 0 : static bool dw8250_detect_rs485_hw(struct uart_port *p)
227 : {
228 0 : u32 reg;
229 :
230 0 : dw8250_writel_ext(p, DW_UART_RE_EN, 1);
231 0 : reg = dw8250_readl_ext(p, DW_UART_RE_EN);
232 0 : dw8250_writel_ext(p, DW_UART_RE_EN, 0);
233 0 : return reg;
234 0 : }
235 :
236 : static const struct serial_rs485 dw8250_rs485_supported = {
237 : .flags = SER_RS485_ENABLED | SER_RS485_RX_DURING_TX | SER_RS485_RTS_ON_SEND |
238 : SER_RS485_RTS_AFTER_SEND | SER_RS485_ADDRB | SER_RS485_ADDR_RECV |
239 : SER_RS485_ADDR_DEST,
240 : };
241 :
242 0 : void dw8250_setup_port(struct uart_port *p)
243 : {
244 0 : struct dw8250_port_data *pd = p->private_data;
245 0 : struct uart_8250_port *up = up_to_u8250p(p);
246 0 : u32 reg, old_dlf;
247 :
248 0 : pd->hw_rs485_support = dw8250_detect_rs485_hw(p);
249 0 : if (pd->hw_rs485_support) {
250 0 : p->rs485_config = dw8250_rs485_config;
251 0 : up->lsr_save_mask = LSR_SAVE_FLAGS | DW_UART_LSR_ADDR_RCVD;
252 0 : p->rs485_supported = dw8250_rs485_supported;
253 0 : } else {
254 0 : p->rs485_config = serial8250_em485_config;
255 0 : p->rs485_supported = serial8250_em485_supported;
256 0 : up->rs485_start_tx = serial8250_em485_start_tx;
257 0 : up->rs485_stop_tx = serial8250_em485_stop_tx;
258 : }
259 0 : up->capabilities |= UART_CAP_NOTEMT;
260 :
261 : /* Preserve value written by firmware or bootloader */
262 0 : old_dlf = dw8250_readl_ext(p, DW_UART_DLF);
263 0 : dw8250_writel_ext(p, DW_UART_DLF, ~0U);
264 0 : reg = dw8250_readl_ext(p, DW_UART_DLF);
265 0 : dw8250_writel_ext(p, DW_UART_DLF, old_dlf);
266 :
267 0 : if (reg) {
268 0 : pd->dlf_size = fls(reg);
269 0 : p->get_divisor = dw8250_get_divisor;
270 0 : p->set_divisor = dw8250_set_divisor;
271 0 : }
272 :
273 0 : reg = dw8250_readl_ext(p, DW_UART_UCV);
274 0 : if (reg)
275 0 : dev_dbg(p->dev, "Designware UART version %c.%c%c\n",
276 : (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
277 :
278 0 : reg = dw8250_readl_ext(p, DW_UART_CPR);
279 0 : if (!reg) {
280 0 : reg = pd->cpr_value;
281 : dev_dbg(p->dev, "CPR is not available, using 0x%08x instead\n", reg);
282 0 : }
283 0 : if (!reg)
284 0 : return;
285 :
286 : /* Select the type based on FIFO */
287 0 : if (reg & DW_UART_CPR_FIFO_MODE) {
288 0 : p->type = PORT_16550A;
289 0 : p->flags |= UPF_FIXED_TYPE;
290 0 : p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
291 0 : up->capabilities = UART_CAP_FIFO | UART_CAP_NOTEMT;
292 0 : }
293 :
294 0 : if (reg & DW_UART_CPR_AFCE_MODE)
295 0 : up->capabilities |= UART_CAP_AFE;
296 :
297 0 : if (reg & DW_UART_CPR_SIR_MODE)
298 0 : up->capabilities |= UART_CAP_IRDA;
299 0 : }
300 : EXPORT_SYMBOL_GPL(dw8250_setup_port);
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