Line data Source code
1 : // SPDX-License-Identifier: GPL-2.0+
2 : /*
3 : * Base port operations for 8250/16550-type serial ports
4 : *
5 : * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 : * Split from 8250_core.c, Copyright (C) 2001 Russell King.
7 : *
8 : * A note about mapbase / membase
9 : *
10 : * mapbase is the physical address of the IO port.
11 : * membase is an 'ioremapped' cookie.
12 : */
13 :
14 : #include <linux/module.h>
15 : #include <linux/moduleparam.h>
16 : #include <linux/ioport.h>
17 : #include <linux/init.h>
18 : #include <linux/irq.h>
19 : #include <linux/console.h>
20 : #include <linux/gpio/consumer.h>
21 : #include <linux/sysrq.h>
22 : #include <linux/delay.h>
23 : #include <linux/platform_device.h>
24 : #include <linux/tty.h>
25 : #include <linux/ratelimit.h>
26 : #include <linux/tty_flip.h>
27 : #include <linux/serial.h>
28 : #include <linux/serial_8250.h>
29 : #include <linux/nmi.h>
30 : #include <linux/mutex.h>
31 : #include <linux/slab.h>
32 : #include <linux/uaccess.h>
33 : #include <linux/pm_runtime.h>
34 : #include <linux/ktime.h>
35 :
36 : #include <asm/io.h>
37 : #include <asm/irq.h>
38 :
39 : #include "8250.h"
40 :
41 : /*
42 : * Here we define the default xmit fifo size used for each type of UART.
43 : */
44 : static const struct serial8250_config uart_config[] = {
45 : [PORT_UNKNOWN] = {
46 : .name = "unknown",
47 : .fifo_size = 1,
48 : .tx_loadsz = 1,
49 : },
50 : [PORT_8250] = {
51 : .name = "8250",
52 : .fifo_size = 1,
53 : .tx_loadsz = 1,
54 : },
55 : [PORT_16450] = {
56 : .name = "16450",
57 : .fifo_size = 1,
58 : .tx_loadsz = 1,
59 : },
60 : [PORT_16550] = {
61 : .name = "16550",
62 : .fifo_size = 1,
63 : .tx_loadsz = 1,
64 : },
65 : [PORT_16550A] = {
66 : .name = "16550A",
67 : .fifo_size = 16,
68 : .tx_loadsz = 16,
69 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
70 : .rxtrig_bytes = {1, 4, 8, 14},
71 : .flags = UART_CAP_FIFO,
72 : },
73 : [PORT_CIRRUS] = {
74 : .name = "Cirrus",
75 : .fifo_size = 1,
76 : .tx_loadsz = 1,
77 : },
78 : [PORT_16650] = {
79 : .name = "ST16650",
80 : .fifo_size = 1,
81 : .tx_loadsz = 1,
82 : .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
83 : },
84 : [PORT_16650V2] = {
85 : .name = "ST16650V2",
86 : .fifo_size = 32,
87 : .tx_loadsz = 16,
88 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
89 : UART_FCR_T_TRIG_00,
90 : .rxtrig_bytes = {8, 16, 24, 28},
91 : .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
92 : },
93 : [PORT_16750] = {
94 : .name = "TI16750",
95 : .fifo_size = 64,
96 : .tx_loadsz = 64,
97 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
98 : UART_FCR7_64BYTE,
99 : .rxtrig_bytes = {1, 16, 32, 56},
100 : .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
101 : },
102 : [PORT_STARTECH] = {
103 : .name = "Startech",
104 : .fifo_size = 1,
105 : .tx_loadsz = 1,
106 : },
107 : [PORT_16C950] = {
108 : .name = "16C950/954",
109 : .fifo_size = 128,
110 : .tx_loadsz = 128,
111 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
112 : .rxtrig_bytes = {16, 32, 112, 120},
113 : /* UART_CAP_EFR breaks billionon CF bluetooth card. */
114 : .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
115 : },
116 : [PORT_16654] = {
117 : .name = "ST16654",
118 : .fifo_size = 64,
119 : .tx_loadsz = 32,
120 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
121 : UART_FCR_T_TRIG_10,
122 : .rxtrig_bytes = {8, 16, 56, 60},
123 : .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
124 : },
125 : [PORT_16850] = {
126 : .name = "XR16850",
127 : .fifo_size = 128,
128 : .tx_loadsz = 128,
129 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
130 : .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
131 : },
132 : [PORT_RSA] = {
133 : .name = "RSA",
134 : .fifo_size = 2048,
135 : .tx_loadsz = 2048,
136 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
137 : .flags = UART_CAP_FIFO,
138 : },
139 : [PORT_NS16550A] = {
140 : .name = "NS16550A",
141 : .fifo_size = 16,
142 : .tx_loadsz = 16,
143 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
144 : .flags = UART_CAP_FIFO | UART_NATSEMI,
145 : },
146 : [PORT_XSCALE] = {
147 : .name = "XScale",
148 : .fifo_size = 32,
149 : .tx_loadsz = 32,
150 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
151 : .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
152 : },
153 : [PORT_OCTEON] = {
154 : .name = "OCTEON",
155 : .fifo_size = 64,
156 : .tx_loadsz = 64,
157 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
158 : .flags = UART_CAP_FIFO,
159 : },
160 : [PORT_U6_16550A] = {
161 : .name = "U6_16550A",
162 : .fifo_size = 64,
163 : .tx_loadsz = 64,
164 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
165 : .flags = UART_CAP_FIFO | UART_CAP_AFE,
166 : },
167 : [PORT_TEGRA] = {
168 : .name = "Tegra",
169 : .fifo_size = 32,
170 : .tx_loadsz = 8,
171 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
172 : UART_FCR_T_TRIG_01,
173 : .rxtrig_bytes = {1, 4, 8, 14},
174 : .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
175 : },
176 : [PORT_XR17D15X] = {
177 : .name = "XR17D15X",
178 : .fifo_size = 64,
179 : .tx_loadsz = 64,
180 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
181 : .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
182 : UART_CAP_SLEEP,
183 : },
184 : [PORT_XR17V35X] = {
185 : .name = "XR17V35X",
186 : .fifo_size = 256,
187 : .tx_loadsz = 256,
188 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
189 : UART_FCR_T_TRIG_11,
190 : .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
191 : UART_CAP_SLEEP,
192 : },
193 : [PORT_LPC3220] = {
194 : .name = "LPC3220",
195 : .fifo_size = 64,
196 : .tx_loadsz = 32,
197 : .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
198 : UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
199 : .flags = UART_CAP_FIFO,
200 : },
201 : [PORT_BRCM_TRUMANAGE] = {
202 : .name = "TruManage",
203 : .fifo_size = 1,
204 : .tx_loadsz = 1024,
205 : .flags = UART_CAP_HFIFO,
206 : },
207 : [PORT_8250_CIR] = {
208 : .name = "CIR port"
209 : },
210 : [PORT_ALTR_16550_F32] = {
211 : .name = "Altera 16550 FIFO32",
212 : .fifo_size = 32,
213 : .tx_loadsz = 32,
214 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
215 : .rxtrig_bytes = {1, 8, 16, 30},
216 : .flags = UART_CAP_FIFO | UART_CAP_AFE,
217 : },
218 : [PORT_ALTR_16550_F64] = {
219 : .name = "Altera 16550 FIFO64",
220 : .fifo_size = 64,
221 : .tx_loadsz = 64,
222 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
223 : .rxtrig_bytes = {1, 16, 32, 62},
224 : .flags = UART_CAP_FIFO | UART_CAP_AFE,
225 : },
226 : [PORT_ALTR_16550_F128] = {
227 : .name = "Altera 16550 FIFO128",
228 : .fifo_size = 128,
229 : .tx_loadsz = 128,
230 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
231 : .rxtrig_bytes = {1, 32, 64, 126},
232 : .flags = UART_CAP_FIFO | UART_CAP_AFE,
233 : },
234 : /*
235 : * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
236 : * workaround of errata A-008006 which states that tx_loadsz should
237 : * be configured less than Maximum supported fifo bytes.
238 : */
239 : [PORT_16550A_FSL64] = {
240 : .name = "16550A_FSL64",
241 : .fifo_size = 64,
242 : .tx_loadsz = 63,
243 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
244 : UART_FCR7_64BYTE,
245 : .flags = UART_CAP_FIFO | UART_CAP_NOTEMT,
246 : },
247 : [PORT_RT2880] = {
248 : .name = "Palmchip BK-3103",
249 : .fifo_size = 16,
250 : .tx_loadsz = 16,
251 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 : .rxtrig_bytes = {1, 4, 8, 14},
253 : .flags = UART_CAP_FIFO,
254 : },
255 : [PORT_DA830] = {
256 : .name = "TI DA8xx/66AK2x",
257 : .fifo_size = 16,
258 : .tx_loadsz = 16,
259 : .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
260 : UART_FCR_R_TRIG_10,
261 : .rxtrig_bytes = {1, 4, 8, 14},
262 : .flags = UART_CAP_FIFO | UART_CAP_AFE,
263 : },
264 : [PORT_MTK_BTIF] = {
265 : .name = "MediaTek BTIF",
266 : .fifo_size = 16,
267 : .tx_loadsz = 16,
268 : .fcr = UART_FCR_ENABLE_FIFO |
269 : UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
270 : .flags = UART_CAP_FIFO,
271 : },
272 : [PORT_NPCM] = {
273 : .name = "Nuvoton 16550",
274 : .fifo_size = 16,
275 : .tx_loadsz = 16,
276 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
277 : UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
278 : .rxtrig_bytes = {1, 4, 8, 14},
279 : .flags = UART_CAP_FIFO,
280 : },
281 : [PORT_SUNIX] = {
282 : .name = "Sunix",
283 : .fifo_size = 128,
284 : .tx_loadsz = 128,
285 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
286 : .rxtrig_bytes = {1, 32, 64, 112},
287 : .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
288 : },
289 : [PORT_ASPEED_VUART] = {
290 : .name = "ASPEED VUART",
291 : .fifo_size = 16,
292 : .tx_loadsz = 16,
293 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
294 : .rxtrig_bytes = {1, 4, 8, 14},
295 : .flags = UART_CAP_FIFO,
296 : },
297 : [PORT_MCHP16550A] = {
298 : .name = "MCHP16550A",
299 : .fifo_size = 256,
300 : .tx_loadsz = 256,
301 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
302 : .rxtrig_bytes = {2, 66, 130, 194},
303 : .flags = UART_CAP_FIFO,
304 : },
305 : [PORT_BCM7271] = {
306 : .name = "Broadcom BCM7271 UART",
307 : .fifo_size = 32,
308 : .tx_loadsz = 32,
309 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
310 : .rxtrig_bytes = {1, 8, 16, 30},
311 : .flags = UART_CAP_FIFO | UART_CAP_AFE,
312 : },
313 : };
314 :
315 : /* Uart divisor latch read */
316 0 : static u32 default_serial_dl_read(struct uart_8250_port *up)
317 : {
318 : /* Assign these in pieces to truncate any bits above 7. */
319 0 : unsigned char dll = serial_in(up, UART_DLL);
320 0 : unsigned char dlm = serial_in(up, UART_DLM);
321 :
322 0 : return dll | dlm << 8;
323 0 : }
324 :
325 : /* Uart divisor latch write */
326 0 : static void default_serial_dl_write(struct uart_8250_port *up, u32 value)
327 : {
328 0 : serial_out(up, UART_DLL, value & 0xff);
329 0 : serial_out(up, UART_DLM, value >> 8 & 0xff);
330 0 : }
331 :
332 : #ifdef CONFIG_HAS_IOPORT
333 0 : static u32 hub6_serial_in(struct uart_port *p, unsigned int offset)
334 : {
335 0 : offset = offset << p->regshift;
336 0 : outb(p->hub6 - 1 + offset, p->iobase);
337 0 : return inb(p->iobase + 1);
338 : }
339 :
340 0 : static void hub6_serial_out(struct uart_port *p, unsigned int offset, u32 value)
341 : {
342 0 : offset = offset << p->regshift;
343 0 : outb(p->hub6 - 1 + offset, p->iobase);
344 0 : outb(value, p->iobase + 1);
345 0 : }
346 : #endif /* CONFIG_HAS_IOPORT */
347 :
348 0 : static u32 mem_serial_in(struct uart_port *p, unsigned int offset)
349 : {
350 0 : offset = offset << p->regshift;
351 0 : return readb(p->membase + offset);
352 : }
353 :
354 0 : static void mem_serial_out(struct uart_port *p, unsigned int offset, u32 value)
355 : {
356 0 : offset = offset << p->regshift;
357 0 : writeb(value, p->membase + offset);
358 0 : }
359 :
360 0 : static void mem16_serial_out(struct uart_port *p, unsigned int offset, u32 value)
361 : {
362 0 : offset = offset << p->regshift;
363 0 : writew(value, p->membase + offset);
364 0 : }
365 :
366 0 : static u32 mem16_serial_in(struct uart_port *p, unsigned int offset)
367 : {
368 0 : offset = offset << p->regshift;
369 0 : return readw(p->membase + offset);
370 : }
371 :
372 0 : static void mem32_serial_out(struct uart_port *p, unsigned int offset, u32 value)
373 : {
374 0 : offset = offset << p->regshift;
375 0 : writel(value, p->membase + offset);
376 0 : }
377 :
378 0 : static u32 mem32_serial_in(struct uart_port *p, unsigned int offset)
379 : {
380 0 : offset = offset << p->regshift;
381 0 : return readl(p->membase + offset);
382 : }
383 :
384 0 : static void mem32be_serial_out(struct uart_port *p, unsigned int offset, u32 value)
385 : {
386 0 : offset = offset << p->regshift;
387 0 : iowrite32be(value, p->membase + offset);
388 0 : }
389 :
390 0 : static u32 mem32be_serial_in(struct uart_port *p, unsigned int offset)
391 : {
392 0 : offset = offset << p->regshift;
393 0 : return ioread32be(p->membase + offset);
394 : }
395 :
396 : #ifdef CONFIG_HAS_IOPORT
397 0 : static u32 io_serial_in(struct uart_port *p, unsigned int offset)
398 : {
399 0 : offset = offset << p->regshift;
400 0 : return inb(p->iobase + offset);
401 : }
402 :
403 0 : static void io_serial_out(struct uart_port *p, unsigned int offset, u32 value)
404 : {
405 0 : offset = offset << p->regshift;
406 0 : outb(value, p->iobase + offset);
407 0 : }
408 : #endif
409 0 : static u32 no_serial_in(struct uart_port *p, unsigned int offset)
410 : {
411 0 : return ~0U;
412 : }
413 :
414 0 : static void no_serial_out(struct uart_port *p, unsigned int offset, u32 value)
415 : {
416 0 : }
417 :
418 : static int serial8250_default_handle_irq(struct uart_port *port);
419 :
420 0 : static void set_io_from_upio(struct uart_port *p)
421 : {
422 0 : struct uart_8250_port *up = up_to_u8250p(p);
423 :
424 0 : up->dl_read = default_serial_dl_read;
425 0 : up->dl_write = default_serial_dl_write;
426 :
427 0 : switch (p->iotype) {
428 : #ifdef CONFIG_HAS_IOPORT
429 : case UPIO_HUB6:
430 0 : p->serial_in = hub6_serial_in;
431 0 : p->serial_out = hub6_serial_out;
432 0 : break;
433 : #endif
434 :
435 : case UPIO_MEM:
436 0 : p->serial_in = mem_serial_in;
437 0 : p->serial_out = mem_serial_out;
438 0 : break;
439 :
440 : case UPIO_MEM16:
441 0 : p->serial_in = mem16_serial_in;
442 0 : p->serial_out = mem16_serial_out;
443 0 : break;
444 :
445 : case UPIO_MEM32:
446 0 : p->serial_in = mem32_serial_in;
447 0 : p->serial_out = mem32_serial_out;
448 0 : break;
449 :
450 : case UPIO_MEM32BE:
451 0 : p->serial_in = mem32be_serial_in;
452 0 : p->serial_out = mem32be_serial_out;
453 0 : break;
454 : #ifdef CONFIG_HAS_IOPORT
455 : case UPIO_PORT:
456 0 : p->serial_in = io_serial_in;
457 0 : p->serial_out = io_serial_out;
458 0 : break;
459 : #endif
460 : default:
461 0 : WARN(p->iotype != UPIO_PORT || p->iobase,
462 : "Unsupported UART type %x\n", p->iotype);
463 0 : p->serial_in = no_serial_in;
464 0 : p->serial_out = no_serial_out;
465 0 : }
466 : /* Remember loaded iotype */
467 0 : up->cur_iotype = p->iotype;
468 0 : p->handle_irq = serial8250_default_handle_irq;
469 0 : }
470 :
471 : static void
472 0 : serial_port_out_sync(struct uart_port *p, int offset, int value)
473 : {
474 0 : switch (p->iotype) {
475 : case UPIO_MEM:
476 : case UPIO_MEM16:
477 : case UPIO_MEM32:
478 : case UPIO_MEM32BE:
479 : case UPIO_AU:
480 0 : p->serial_out(p, offset, value);
481 0 : p->serial_in(p, UART_LCR); /* safe, no side-effects */
482 0 : break;
483 : default:
484 0 : p->serial_out(p, offset, value);
485 0 : }
486 0 : }
487 :
488 : /*
489 : * FIFO support.
490 : */
491 0 : static void serial8250_clear_fifos(struct uart_8250_port *p)
492 : {
493 0 : if (p->capabilities & UART_CAP_FIFO) {
494 0 : serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
495 0 : serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
496 : UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
497 0 : serial_out(p, UART_FCR, 0);
498 0 : }
499 0 : }
500 :
501 : static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
502 : static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
503 :
504 0 : void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
505 : {
506 0 : serial8250_clear_fifos(p);
507 0 : serial_out(p, UART_FCR, p->fcr);
508 0 : }
509 : EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
510 :
511 0 : static void serial8250_rpm_get(struct uart_8250_port *p)
512 : {
513 0 : if (!(p->capabilities & UART_CAP_RPM))
514 0 : return;
515 0 : pm_runtime_get_sync(p->port.dev);
516 0 : }
517 :
518 0 : static void serial8250_rpm_put(struct uart_8250_port *p)
519 : {
520 0 : if (!(p->capabilities & UART_CAP_RPM))
521 0 : return;
522 0 : pm_runtime_mark_last_busy(p->port.dev);
523 0 : pm_runtime_put_autosuspend(p->port.dev);
524 0 : }
525 :
526 : /**
527 : * serial8250_em485_init() - put uart_8250_port into rs485 emulating
528 : * @p: uart_8250_port port instance
529 : *
530 : * The function is used to start rs485 software emulating on the
531 : * &struct uart_8250_port* @p. Namely, RTS is switched before/after
532 : * transmission. The function is idempotent, so it is safe to call it
533 : * multiple times.
534 : *
535 : * The caller MUST enable interrupt on empty shift register before
536 : * calling serial8250_em485_init(). This interrupt is not a part of
537 : * 8250 standard, but implementation defined.
538 : *
539 : * The function is supposed to be called from .rs485_config callback
540 : * or from any other callback protected with p->port.lock spinlock.
541 : *
542 : * See also serial8250_em485_destroy()
543 : *
544 : * Return 0 - success, -errno - otherwise
545 : */
546 0 : static int serial8250_em485_init(struct uart_8250_port *p)
547 : {
548 : /* Port locked to synchronize UART_IER access against the console. */
549 0 : lockdep_assert_held_once(&p->port.lock);
550 :
551 0 : if (p->em485)
552 0 : goto deassert_rts;
553 :
554 0 : p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
555 0 : if (!p->em485)
556 0 : return -ENOMEM;
557 :
558 0 : hrtimer_setup(&p->em485->stop_tx_timer, &serial8250_em485_handle_stop_tx, CLOCK_MONOTONIC,
559 : HRTIMER_MODE_REL);
560 0 : hrtimer_setup(&p->em485->start_tx_timer, &serial8250_em485_handle_start_tx, CLOCK_MONOTONIC,
561 : HRTIMER_MODE_REL);
562 0 : p->em485->port = p;
563 0 : p->em485->active_timer = NULL;
564 0 : p->em485->tx_stopped = true;
565 :
566 : deassert_rts:
567 0 : if (p->em485->tx_stopped)
568 0 : p->rs485_stop_tx(p, true);
569 :
570 0 : return 0;
571 0 : }
572 :
573 : /**
574 : * serial8250_em485_destroy() - put uart_8250_port into normal state
575 : * @p: uart_8250_port port instance
576 : *
577 : * The function is used to stop rs485 software emulating on the
578 : * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
579 : * call it multiple times.
580 : *
581 : * The function is supposed to be called from .rs485_config callback
582 : * or from any other callback protected with p->port.lock spinlock.
583 : *
584 : * See also serial8250_em485_init()
585 : */
586 0 : void serial8250_em485_destroy(struct uart_8250_port *p)
587 : {
588 0 : if (!p->em485)
589 0 : return;
590 :
591 0 : hrtimer_cancel(&p->em485->start_tx_timer);
592 0 : hrtimer_cancel(&p->em485->stop_tx_timer);
593 :
594 0 : kfree(p->em485);
595 0 : p->em485 = NULL;
596 0 : }
597 : EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
598 :
599 : struct serial_rs485 serial8250_em485_supported = {
600 : .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
601 : SER_RS485_TERMINATE_BUS | SER_RS485_RX_DURING_TX,
602 : .delay_rts_before_send = 1,
603 : .delay_rts_after_send = 1,
604 : };
605 : EXPORT_SYMBOL_GPL(serial8250_em485_supported);
606 :
607 : /**
608 : * serial8250_em485_config() - generic ->rs485_config() callback
609 : * @port: uart port
610 : * @termios: termios structure
611 : * @rs485: rs485 settings
612 : *
613 : * Generic callback usable by 8250 uart drivers to activate rs485 settings
614 : * if the uart is incapable of driving RTS as a Transmit Enable signal in
615 : * hardware, relying on software emulation instead.
616 : */
617 0 : int serial8250_em485_config(struct uart_port *port, struct ktermios *termios,
618 : struct serial_rs485 *rs485)
619 : {
620 0 : struct uart_8250_port *up = up_to_u8250p(port);
621 :
622 : /*
623 : * Both serial8250_em485_init() and serial8250_em485_destroy()
624 : * are idempotent.
625 : */
626 0 : if (rs485->flags & SER_RS485_ENABLED)
627 0 : return serial8250_em485_init(up);
628 :
629 0 : serial8250_em485_destroy(up);
630 0 : return 0;
631 0 : }
632 : EXPORT_SYMBOL_GPL(serial8250_em485_config);
633 :
634 : /*
635 : * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
636 : * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
637 : * empty and the HW can idle again.
638 : */
639 0 : static void serial8250_rpm_get_tx(struct uart_8250_port *p)
640 : {
641 0 : unsigned char rpm_active;
642 :
643 0 : if (!(p->capabilities & UART_CAP_RPM))
644 0 : return;
645 :
646 0 : rpm_active = xchg(&p->rpm_tx_active, 1);
647 0 : if (rpm_active)
648 0 : return;
649 0 : pm_runtime_get_sync(p->port.dev);
650 0 : }
651 :
652 0 : static void serial8250_rpm_put_tx(struct uart_8250_port *p)
653 : {
654 0 : unsigned char rpm_active;
655 :
656 0 : if (!(p->capabilities & UART_CAP_RPM))
657 0 : return;
658 :
659 0 : rpm_active = xchg(&p->rpm_tx_active, 0);
660 0 : if (!rpm_active)
661 0 : return;
662 0 : pm_runtime_mark_last_busy(p->port.dev);
663 0 : pm_runtime_put_autosuspend(p->port.dev);
664 0 : }
665 :
666 : /*
667 : * IER sleep support. UARTs which have EFRs need the "extended
668 : * capability" bit enabled. Note that on XR16C850s, we need to
669 : * reset LCR to write to IER.
670 : */
671 0 : static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
672 : {
673 0 : unsigned char lcr = 0, efr = 0;
674 :
675 0 : serial8250_rpm_get(p);
676 :
677 0 : if (p->capabilities & UART_CAP_SLEEP) {
678 : /* Synchronize UART_IER access against the console. */
679 0 : uart_port_lock_irq(&p->port);
680 0 : if (p->capabilities & UART_CAP_EFR) {
681 0 : lcr = serial_in(p, UART_LCR);
682 0 : efr = serial_in(p, UART_EFR);
683 0 : serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
684 0 : serial_out(p, UART_EFR, UART_EFR_ECB);
685 0 : serial_out(p, UART_LCR, 0);
686 0 : }
687 0 : serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
688 0 : if (p->capabilities & UART_CAP_EFR) {
689 0 : serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
690 0 : serial_out(p, UART_EFR, efr);
691 0 : serial_out(p, UART_LCR, lcr);
692 0 : }
693 0 : uart_port_unlock_irq(&p->port);
694 0 : }
695 :
696 0 : serial8250_rpm_put(p);
697 0 : }
698 :
699 : /* Clear the interrupt registers. */
700 0 : static void serial8250_clear_interrupts(struct uart_port *port)
701 : {
702 0 : serial_port_in(port, UART_LSR);
703 0 : serial_port_in(port, UART_RX);
704 0 : serial_port_in(port, UART_IIR);
705 0 : serial_port_in(port, UART_MSR);
706 0 : }
707 :
708 0 : static void serial8250_clear_IER(struct uart_8250_port *up)
709 : {
710 0 : if (up->capabilities & UART_CAP_UUE)
711 0 : serial_out(up, UART_IER, UART_IER_UUE);
712 : else
713 0 : serial_out(up, UART_IER, 0);
714 0 : }
715 :
716 : /*
717 : * This is a quickie test to see how big the FIFO is.
718 : * It doesn't work at all the time, more's the pity.
719 : */
720 0 : static int size_fifo(struct uart_8250_port *up)
721 : {
722 0 : unsigned char old_fcr, old_mcr, old_lcr;
723 0 : u32 old_dl;
724 0 : int count;
725 :
726 0 : old_lcr = serial_in(up, UART_LCR);
727 0 : serial_out(up, UART_LCR, 0);
728 0 : old_fcr = serial_in(up, UART_FCR);
729 0 : old_mcr = serial8250_in_MCR(up);
730 0 : serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
731 : UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
732 0 : serial8250_out_MCR(up, UART_MCR_LOOP);
733 0 : serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
734 0 : old_dl = serial_dl_read(up);
735 0 : serial_dl_write(up, 0x0001);
736 0 : serial_out(up, UART_LCR, UART_LCR_WLEN8);
737 0 : for (count = 0; count < 256; count++)
738 0 : serial_out(up, UART_TX, count);
739 0 : mdelay(20);/* FIXME - schedule_timeout */
740 0 : for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
741 0 : (count < 256); count++)
742 0 : serial_in(up, UART_RX);
743 0 : serial_out(up, UART_FCR, old_fcr);
744 0 : serial8250_out_MCR(up, old_mcr);
745 0 : serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
746 0 : serial_dl_write(up, old_dl);
747 0 : serial_out(up, UART_LCR, old_lcr);
748 :
749 0 : return count;
750 0 : }
751 :
752 : /*
753 : * Read UART ID using the divisor method - set DLL and DLM to zero
754 : * and the revision will be in DLL and device type in DLM. We
755 : * preserve the device state across this.
756 : */
757 0 : static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
758 : {
759 0 : unsigned char old_lcr;
760 0 : unsigned int id, old_dl;
761 :
762 0 : old_lcr = serial_in(p, UART_LCR);
763 0 : serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
764 0 : old_dl = serial_dl_read(p);
765 0 : serial_dl_write(p, 0);
766 0 : id = serial_dl_read(p);
767 0 : serial_dl_write(p, old_dl);
768 :
769 0 : serial_out(p, UART_LCR, old_lcr);
770 :
771 0 : return id;
772 0 : }
773 :
774 : /*
775 : * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
776 : * When this function is called we know it is at least a StarTech
777 : * 16650 V2, but it might be one of several StarTech UARTs, or one of
778 : * its clones. (We treat the broken original StarTech 16650 V1 as a
779 : * 16550, and why not? Startech doesn't seem to even acknowledge its
780 : * existence.)
781 : *
782 : * What evil have men's minds wrought...
783 : */
784 0 : static void autoconfig_has_efr(struct uart_8250_port *up)
785 : {
786 0 : unsigned int id1, id2, id3, rev;
787 :
788 : /*
789 : * Everything with an EFR has SLEEP
790 : */
791 0 : up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
792 :
793 : /*
794 : * First we check to see if it's an Oxford Semiconductor UART.
795 : *
796 : * If we have to do this here because some non-National
797 : * Semiconductor clone chips lock up if you try writing to the
798 : * LSR register (which serial_icr_read does)
799 : */
800 :
801 : /*
802 : * Check for Oxford Semiconductor 16C950.
803 : *
804 : * EFR [4] must be set else this test fails.
805 : *
806 : * This shouldn't be necessary, but Mike Hudson ([email protected])
807 : * claims that it's needed for 952 dual UART's (which are not
808 : * recommended for new designs).
809 : */
810 0 : up->acr = 0;
811 0 : serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
812 0 : serial_out(up, UART_EFR, UART_EFR_ECB);
813 0 : serial_out(up, UART_LCR, 0x00);
814 0 : id1 = serial_icr_read(up, UART_ID1);
815 0 : id2 = serial_icr_read(up, UART_ID2);
816 0 : id3 = serial_icr_read(up, UART_ID3);
817 0 : rev = serial_icr_read(up, UART_REV);
818 :
819 0 : if (id1 == 0x16 && id2 == 0xC9 &&
820 0 : (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
821 0 : up->port.type = PORT_16C950;
822 :
823 : /*
824 : * Enable work around for the Oxford Semiconductor 952 rev B
825 : * chip which causes it to seriously miscalculate baud rates
826 : * when DLL is 0.
827 : */
828 0 : if (id3 == 0x52 && rev == 0x01)
829 0 : up->bugs |= UART_BUG_QUOT;
830 0 : return;
831 : }
832 :
833 : /*
834 : * We check for a XR16C850 by setting DLL and DLM to 0, and then
835 : * reading back DLL and DLM. The chip type depends on the DLM
836 : * value read back:
837 : * 0x10 - XR16C850 and the DLL contains the chip revision.
838 : * 0x12 - XR16C2850.
839 : * 0x14 - XR16C854.
840 : */
841 0 : id1 = autoconfig_read_divisor_id(up);
842 :
843 0 : id2 = id1 >> 8;
844 0 : if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
845 0 : up->port.type = PORT_16850;
846 0 : return;
847 : }
848 :
849 : /*
850 : * It wasn't an XR16C850.
851 : *
852 : * We distinguish between the '654 and the '650 by counting
853 : * how many bytes are in the FIFO. I'm using this for now,
854 : * since that's the technique that was sent to me in the
855 : * serial driver update, but I'm not convinced this works.
856 : * I've had problems doing this in the past. -TYT
857 : */
858 0 : if (size_fifo(up) == 64)
859 0 : up->port.type = PORT_16654;
860 : else
861 0 : up->port.type = PORT_16650V2;
862 0 : }
863 :
864 : /*
865 : * We detected a chip without a FIFO. Only two fall into
866 : * this category - the original 8250 and the 16450. The
867 : * 16450 has a scratch register (accessible with LCR=0)
868 : */
869 0 : static void autoconfig_8250(struct uart_8250_port *up)
870 : {
871 0 : unsigned char scratch, status1, status2;
872 :
873 0 : up->port.type = PORT_8250;
874 :
875 0 : scratch = serial_in(up, UART_SCR);
876 0 : serial_out(up, UART_SCR, 0xa5);
877 0 : status1 = serial_in(up, UART_SCR);
878 0 : serial_out(up, UART_SCR, 0x5a);
879 0 : status2 = serial_in(up, UART_SCR);
880 0 : serial_out(up, UART_SCR, scratch);
881 :
882 0 : if (status1 == 0xa5 && status2 == 0x5a)
883 0 : up->port.type = PORT_16450;
884 0 : }
885 :
886 0 : static int broken_efr(struct uart_8250_port *up)
887 : {
888 : /*
889 : * Exar ST16C2550 "A2" devices incorrectly detect as
890 : * having an EFR, and report an ID of 0x0201. See
891 : * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
892 : */
893 0 : if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
894 0 : return 1;
895 :
896 0 : return 0;
897 0 : }
898 :
899 : /*
900 : * We know that the chip has FIFOs. Does it have an EFR? The
901 : * EFR is located in the same register position as the IIR and
902 : * we know the top two bits of the IIR are currently set. The
903 : * EFR should contain zero. Try to read the EFR.
904 : */
905 0 : static void autoconfig_16550a(struct uart_8250_port *up)
906 : {
907 0 : unsigned char status1, status2;
908 0 : unsigned int iersave;
909 :
910 : /* Port locked to synchronize UART_IER access against the console. */
911 0 : lockdep_assert_held_once(&up->port.lock);
912 :
913 0 : up->port.type = PORT_16550A;
914 0 : up->capabilities |= UART_CAP_FIFO;
915 :
916 0 : if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS) &&
917 0 : !(up->port.flags & UPF_FULL_PROBE))
918 0 : return;
919 :
920 : /*
921 : * Check for presence of the EFR when DLAB is set.
922 : * Only ST16C650V1 UARTs pass this test.
923 : */
924 0 : serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
925 0 : if (serial_in(up, UART_EFR) == 0) {
926 0 : serial_out(up, UART_EFR, 0xA8);
927 0 : if (serial_in(up, UART_EFR) != 0) {
928 0 : up->port.type = PORT_16650;
929 0 : up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
930 0 : } else {
931 0 : serial_out(up, UART_LCR, 0);
932 0 : serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
933 : UART_FCR7_64BYTE);
934 0 : status1 = serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED_16750;
935 0 : serial_out(up, UART_FCR, 0);
936 0 : serial_out(up, UART_LCR, 0);
937 :
938 0 : if (status1 == UART_IIR_FIFO_ENABLED_16750)
939 0 : up->port.type = PORT_16550A_FSL64;
940 : }
941 0 : serial_out(up, UART_EFR, 0);
942 0 : return;
943 : }
944 :
945 : /*
946 : * Maybe it requires 0xbf to be written to the LCR.
947 : * (other ST16C650V2 UARTs, TI16C752A, etc)
948 : */
949 0 : serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
950 0 : if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
951 0 : autoconfig_has_efr(up);
952 0 : return;
953 : }
954 :
955 : /*
956 : * Check for a National Semiconductor SuperIO chip.
957 : * Attempt to switch to bank 2, read the value of the LOOP bit
958 : * from EXCR1. Switch back to bank 0, change it in MCR. Then
959 : * switch back to bank 2, read it from EXCR1 again and check
960 : * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
961 : */
962 0 : serial_out(up, UART_LCR, 0);
963 0 : status1 = serial8250_in_MCR(up);
964 0 : serial_out(up, UART_LCR, 0xE0);
965 0 : status2 = serial_in(up, 0x02); /* EXCR1 */
966 :
967 0 : if (!((status2 ^ status1) & UART_MCR_LOOP)) {
968 0 : serial_out(up, UART_LCR, 0);
969 0 : serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
970 0 : serial_out(up, UART_LCR, 0xE0);
971 0 : status2 = serial_in(up, 0x02); /* EXCR1 */
972 0 : serial_out(up, UART_LCR, 0);
973 0 : serial8250_out_MCR(up, status1);
974 :
975 0 : if ((status2 ^ status1) & UART_MCR_LOOP) {
976 0 : unsigned short quot;
977 :
978 0 : serial_out(up, UART_LCR, 0xE0);
979 :
980 0 : quot = serial_dl_read(up);
981 0 : quot <<= 3;
982 :
983 0 : if (ns16550a_goto_highspeed(up))
984 0 : serial_dl_write(up, quot);
985 :
986 0 : serial_out(up, UART_LCR, 0);
987 :
988 0 : up->port.uartclk = 921600*16;
989 0 : up->port.type = PORT_NS16550A;
990 0 : up->capabilities |= UART_NATSEMI;
991 : return;
992 0 : }
993 0 : }
994 :
995 : /*
996 : * No EFR. Try to detect a TI16750, which only sets bit 5 of
997 : * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
998 : * Try setting it with and without DLAB set. Cheap clones
999 : * set bit 5 without DLAB set.
1000 : */
1001 0 : serial_out(up, UART_LCR, 0);
1002 0 : serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1003 0 : status1 = serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED_16750;
1004 0 : serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1005 :
1006 0 : serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1007 0 : serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1008 0 : status2 = serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED_16750;
1009 0 : serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1010 :
1011 0 : serial_out(up, UART_LCR, 0);
1012 :
1013 0 : if (status1 == UART_IIR_FIFO_ENABLED_16550A &&
1014 0 : status2 == UART_IIR_FIFO_ENABLED_16750) {
1015 0 : up->port.type = PORT_16750;
1016 0 : up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1017 0 : return;
1018 : }
1019 :
1020 : /*
1021 : * Try writing and reading the UART_IER_UUE bit (b6).
1022 : * If it works, this is probably one of the Xscale platform's
1023 : * internal UARTs.
1024 : * We're going to explicitly set the UUE bit to 0 before
1025 : * trying to write and read a 1 just to make sure it's not
1026 : * already a 1 and maybe locked there before we even start.
1027 : */
1028 0 : iersave = serial_in(up, UART_IER);
1029 0 : serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1030 0 : if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1031 : /*
1032 : * OK it's in a known zero state, try writing and reading
1033 : * without disturbing the current state of the other bits.
1034 : */
1035 0 : serial_out(up, UART_IER, iersave | UART_IER_UUE);
1036 0 : if (serial_in(up, UART_IER) & UART_IER_UUE) {
1037 : /*
1038 : * It's an Xscale.
1039 : * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1040 : */
1041 0 : up->port.type = PORT_XSCALE;
1042 0 : up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1043 0 : return;
1044 : }
1045 0 : }
1046 0 : serial_out(up, UART_IER, iersave);
1047 :
1048 : /*
1049 : * We distinguish between 16550A and U6 16550A by counting
1050 : * how many bytes are in the FIFO.
1051 : */
1052 0 : if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1053 0 : up->port.type = PORT_U6_16550A;
1054 0 : up->capabilities |= UART_CAP_AFE;
1055 0 : }
1056 0 : }
1057 :
1058 : /*
1059 : * This routine is called by rs_init() to initialize a specific serial
1060 : * port. It determines what type of UART chip this serial port is
1061 : * using: 8250, 16450, 16550, 16550A. The important question is
1062 : * whether or not this UART is a 16550A or not, since this will
1063 : * determine whether or not we can use its FIFO features or not.
1064 : */
1065 0 : static void autoconfig(struct uart_8250_port *up)
1066 : {
1067 0 : unsigned char status1, scratch, scratch2, scratch3;
1068 0 : unsigned char save_lcr, save_mcr;
1069 0 : struct uart_port *port = &up->port;
1070 0 : unsigned long flags;
1071 0 : unsigned int old_capabilities;
1072 :
1073 0 : if (!port->iobase && !port->mapbase && !port->membase)
1074 0 : return;
1075 :
1076 : /*
1077 : * We really do need global IRQs disabled here - we're going to
1078 : * be frobbing the chips IRQ enable register to see if it exists.
1079 : *
1080 : * Synchronize UART_IER access against the console.
1081 : */
1082 0 : uart_port_lock_irqsave(port, &flags);
1083 :
1084 0 : up->capabilities = 0;
1085 0 : up->bugs = 0;
1086 :
1087 0 : if (!(port->flags & UPF_BUGGY_UART)) {
1088 : /*
1089 : * Do a simple existence test first; if we fail this,
1090 : * there's no point trying anything else.
1091 : *
1092 : * 0x80 is used as a nonsense port to prevent against
1093 : * false positives due to ISA bus float. The
1094 : * assumption is that 0x80 is a non-existent port;
1095 : * which should be safe since include/asm/io.h also
1096 : * makes this assumption.
1097 : *
1098 : * Note: this is safe as long as MCR bit 4 is clear
1099 : * and the device is in "PC" mode.
1100 : */
1101 0 : scratch = serial_in(up, UART_IER);
1102 0 : serial_out(up, UART_IER, 0);
1103 : #if defined(__i386__) && defined(CONFIG_HAS_IOPORT)
1104 : outb(0xff, 0x080);
1105 : #endif
1106 : /*
1107 : * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1108 : * 16C754B) allow only to modify them if an EFR bit is set.
1109 : */
1110 0 : scratch2 = serial_in(up, UART_IER) & UART_IER_ALL_INTR;
1111 0 : serial_out(up, UART_IER, UART_IER_ALL_INTR);
1112 : #if defined(__i386__) && defined(CONFIG_HAS_IOPORT)
1113 : outb(0, 0x080);
1114 : #endif
1115 0 : scratch3 = serial_in(up, UART_IER) & UART_IER_ALL_INTR;
1116 0 : serial_out(up, UART_IER, scratch);
1117 0 : if (scratch2 != 0 || scratch3 != UART_IER_ALL_INTR) {
1118 : /*
1119 : * We failed; there's nothing here
1120 : */
1121 0 : uart_port_unlock_irqrestore(port, flags);
1122 0 : return;
1123 : }
1124 0 : }
1125 :
1126 0 : save_mcr = serial8250_in_MCR(up);
1127 0 : save_lcr = serial_in(up, UART_LCR);
1128 :
1129 : /*
1130 : * Check to see if a UART is really there. Certain broken
1131 : * internal modems based on the Rockwell chipset fail this
1132 : * test, because they apparently don't implement the loopback
1133 : * test mode. So this test is skipped on the COM 1 through
1134 : * COM 4 ports. This *should* be safe, since no board
1135 : * manufacturer would be stupid enough to design a board
1136 : * that conflicts with COM 1-4 --- we hope!
1137 : */
1138 0 : if (!(port->flags & UPF_SKIP_TEST)) {
1139 0 : serial8250_out_MCR(up, UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_RTS);
1140 0 : status1 = serial_in(up, UART_MSR) & UART_MSR_STATUS_BITS;
1141 0 : serial8250_out_MCR(up, save_mcr);
1142 0 : if (status1 != (UART_MSR_DCD | UART_MSR_CTS)) {
1143 0 : uart_port_unlock_irqrestore(port, flags);
1144 0 : return;
1145 : }
1146 0 : }
1147 :
1148 : /*
1149 : * We're pretty sure there's a port here. Lets find out what
1150 : * type of port it is. The IIR top two bits allows us to find
1151 : * out if it's 8250 or 16450, 16550, 16550A or later. This
1152 : * determines what we test for next.
1153 : *
1154 : * We also initialise the EFR (if any) to zero for later. The
1155 : * EFR occupies the same register location as the FCR and IIR.
1156 : */
1157 0 : serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1158 0 : serial_out(up, UART_EFR, 0);
1159 0 : serial_out(up, UART_LCR, 0);
1160 :
1161 0 : serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1162 :
1163 0 : switch (serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED) {
1164 : case UART_IIR_FIFO_ENABLED_8250:
1165 0 : autoconfig_8250(up);
1166 0 : break;
1167 : case UART_IIR_FIFO_ENABLED_16550:
1168 0 : port->type = PORT_16550;
1169 0 : break;
1170 : case UART_IIR_FIFO_ENABLED_16550A:
1171 0 : autoconfig_16550a(up);
1172 0 : break;
1173 : default:
1174 0 : port->type = PORT_UNKNOWN;
1175 0 : break;
1176 : }
1177 :
1178 0 : rsa_autoconfig(up);
1179 :
1180 0 : serial_out(up, UART_LCR, save_lcr);
1181 :
1182 0 : port->fifosize = uart_config[up->port.type].fifo_size;
1183 0 : old_capabilities = up->capabilities;
1184 0 : up->capabilities = uart_config[port->type].flags;
1185 0 : up->tx_loadsz = uart_config[port->type].tx_loadsz;
1186 :
1187 0 : if (port->type != PORT_UNKNOWN) {
1188 : /*
1189 : * Reset the UART.
1190 : */
1191 0 : rsa_reset(up);
1192 0 : serial8250_out_MCR(up, save_mcr);
1193 0 : serial8250_clear_fifos(up);
1194 0 : serial_in(up, UART_RX);
1195 0 : serial8250_clear_IER(up);
1196 0 : }
1197 :
1198 0 : uart_port_unlock_irqrestore(port, flags);
1199 :
1200 : /*
1201 : * Check if the device is a Fintek F81216A
1202 : */
1203 0 : if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1204 0 : fintek_8250_probe(up);
1205 :
1206 0 : if (up->capabilities != old_capabilities) {
1207 0 : dev_warn(port->dev, "detected caps %08x should be %08x\n",
1208 : old_capabilities, up->capabilities);
1209 0 : }
1210 0 : }
1211 :
1212 0 : static void autoconfig_irq(struct uart_8250_port *up)
1213 : {
1214 0 : struct uart_port *port = &up->port;
1215 0 : unsigned char save_mcr, save_ier;
1216 0 : unsigned char save_ICP = 0;
1217 0 : unsigned int ICP = 0;
1218 0 : unsigned long irqs;
1219 0 : int irq;
1220 :
1221 0 : if (port->flags & UPF_FOURPORT) {
1222 0 : ICP = (port->iobase & 0xfe0) | 0x1f;
1223 0 : save_ICP = inb_p(ICP);
1224 0 : outb_p(0x80, ICP);
1225 0 : inb_p(ICP);
1226 0 : }
1227 :
1228 : /* forget possible initially masked and pending IRQ */
1229 0 : probe_irq_off(probe_irq_on());
1230 0 : save_mcr = serial8250_in_MCR(up);
1231 : /* Synchronize UART_IER access against the console. */
1232 0 : uart_port_lock_irq(port);
1233 0 : save_ier = serial_in(up, UART_IER);
1234 0 : uart_port_unlock_irq(port);
1235 0 : serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1236 :
1237 0 : irqs = probe_irq_on();
1238 0 : serial8250_out_MCR(up, 0);
1239 0 : udelay(10);
1240 0 : if (port->flags & UPF_FOURPORT) {
1241 0 : serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1242 0 : } else {
1243 0 : serial8250_out_MCR(up,
1244 : UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1245 : }
1246 : /* Synchronize UART_IER access against the console. */
1247 0 : uart_port_lock_irq(port);
1248 0 : serial_out(up, UART_IER, UART_IER_ALL_INTR);
1249 0 : uart_port_unlock_irq(port);
1250 0 : serial8250_clear_interrupts(port);
1251 0 : serial_out(up, UART_TX, 0xFF);
1252 0 : udelay(20);
1253 0 : irq = probe_irq_off(irqs);
1254 :
1255 0 : serial8250_out_MCR(up, save_mcr);
1256 : /* Synchronize UART_IER access against the console. */
1257 0 : uart_port_lock_irq(port);
1258 0 : serial_out(up, UART_IER, save_ier);
1259 0 : uart_port_unlock_irq(port);
1260 :
1261 0 : if (port->flags & UPF_FOURPORT)
1262 0 : outb_p(save_ICP, ICP);
1263 :
1264 0 : port->irq = (irq > 0) ? irq : 0;
1265 0 : }
1266 :
1267 0 : static void serial8250_stop_rx(struct uart_port *port)
1268 : {
1269 0 : struct uart_8250_port *up = up_to_u8250p(port);
1270 :
1271 : /* Port locked to synchronize UART_IER access against the console. */
1272 0 : lockdep_assert_held_once(&port->lock);
1273 :
1274 0 : serial8250_rpm_get(up);
1275 :
1276 0 : up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1277 0 : serial_port_out(port, UART_IER, up->ier);
1278 :
1279 0 : serial8250_rpm_put(up);
1280 0 : }
1281 :
1282 : /**
1283 : * serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback
1284 : * @p: uart 8250 port
1285 : * @toggle_ier: true to allow enabling receive interrupts
1286 : *
1287 : * Generic callback usable by 8250 uart drivers to stop rs485 transmission.
1288 : */
1289 0 : void serial8250_em485_stop_tx(struct uart_8250_port *p, bool toggle_ier)
1290 : {
1291 0 : unsigned char mcr = serial8250_in_MCR(p);
1292 :
1293 : /* Port locked to synchronize UART_IER access against the console. */
1294 0 : lockdep_assert_held_once(&p->port.lock);
1295 :
1296 0 : if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
1297 0 : mcr |= UART_MCR_RTS;
1298 : else
1299 0 : mcr &= ~UART_MCR_RTS;
1300 0 : serial8250_out_MCR(p, mcr);
1301 :
1302 : /*
1303 : * Empty the RX FIFO, we are not interested in anything
1304 : * received during the half-duplex transmission.
1305 : * Enable previously disabled RX interrupts.
1306 : */
1307 0 : if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1308 0 : serial8250_clear_and_reinit_fifos(p);
1309 :
1310 0 : if (toggle_ier) {
1311 0 : p->ier |= UART_IER_RLSI | UART_IER_RDI;
1312 0 : serial_port_out(&p->port, UART_IER, p->ier);
1313 0 : }
1314 0 : }
1315 0 : }
1316 : EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx);
1317 :
1318 0 : static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1319 : {
1320 0 : struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1321 : stop_tx_timer);
1322 0 : struct uart_8250_port *p = em485->port;
1323 0 : unsigned long flags;
1324 :
1325 0 : serial8250_rpm_get(p);
1326 0 : uart_port_lock_irqsave(&p->port, &flags);
1327 0 : if (em485->active_timer == &em485->stop_tx_timer) {
1328 0 : p->rs485_stop_tx(p, true);
1329 0 : em485->active_timer = NULL;
1330 0 : em485->tx_stopped = true;
1331 0 : }
1332 0 : uart_port_unlock_irqrestore(&p->port, flags);
1333 0 : serial8250_rpm_put(p);
1334 :
1335 0 : return HRTIMER_NORESTART;
1336 0 : }
1337 :
1338 0 : static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1339 : {
1340 0 : hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
1341 0 : }
1342 :
1343 0 : static void __stop_tx_rs485(struct uart_8250_port *p, u64 stop_delay)
1344 : {
1345 0 : struct uart_8250_em485 *em485 = p->em485;
1346 :
1347 : /* Port locked to synchronize UART_IER access against the console. */
1348 0 : lockdep_assert_held_once(&p->port.lock);
1349 :
1350 0 : stop_delay += (u64)p->port.rs485.delay_rts_after_send * NSEC_PER_MSEC;
1351 :
1352 : /*
1353 : * rs485_stop_tx() is going to set RTS according to config
1354 : * AND flush RX FIFO if required.
1355 : */
1356 0 : if (stop_delay > 0) {
1357 0 : em485->active_timer = &em485->stop_tx_timer;
1358 0 : hrtimer_start(&em485->stop_tx_timer, ns_to_ktime(stop_delay), HRTIMER_MODE_REL);
1359 0 : } else {
1360 0 : p->rs485_stop_tx(p, true);
1361 0 : em485->active_timer = NULL;
1362 0 : em485->tx_stopped = true;
1363 : }
1364 0 : }
1365 :
1366 0 : static inline void __stop_tx(struct uart_8250_port *p)
1367 : {
1368 0 : struct uart_8250_em485 *em485 = p->em485;
1369 :
1370 0 : if (em485) {
1371 0 : u16 lsr = serial_lsr_in(p);
1372 0 : u64 stop_delay = 0;
1373 :
1374 0 : if (!(lsr & UART_LSR_THRE))
1375 0 : return;
1376 : /*
1377 : * To provide required timing and allow FIFO transfer,
1378 : * __stop_tx_rs485() must be called only when both FIFO and
1379 : * shift register are empty. The device driver should either
1380 : * enable interrupt on TEMT or set UART_CAP_NOTEMT that will
1381 : * enlarge stop_tx_timer by the tx time of one frame to cover
1382 : * for emptying of the shift register.
1383 : */
1384 0 : if (!(lsr & UART_LSR_TEMT)) {
1385 0 : if (!(p->capabilities & UART_CAP_NOTEMT))
1386 0 : return;
1387 : /*
1388 : * RTS might get deasserted too early with the normal
1389 : * frame timing formula. It seems to suggest THRE might
1390 : * get asserted already during tx of the stop bit
1391 : * rather than after it is fully sent.
1392 : * Roughly estimate 1 extra bit here with / 7.
1393 : */
1394 0 : stop_delay = p->port.frame_time + DIV_ROUND_UP(p->port.frame_time, 7);
1395 0 : }
1396 :
1397 0 : __stop_tx_rs485(p, stop_delay);
1398 0 : }
1399 :
1400 0 : if (serial8250_clear_THRI(p))
1401 0 : serial8250_rpm_put_tx(p);
1402 0 : }
1403 :
1404 0 : static void serial8250_stop_tx(struct uart_port *port)
1405 : {
1406 0 : struct uart_8250_port *up = up_to_u8250p(port);
1407 :
1408 0 : serial8250_rpm_get(up);
1409 0 : __stop_tx(up);
1410 :
1411 : /*
1412 : * We really want to stop the transmitter from sending.
1413 : */
1414 0 : if (port->type == PORT_16C950) {
1415 0 : up->acr |= UART_ACR_TXDIS;
1416 0 : serial_icr_write(up, UART_ACR, up->acr);
1417 0 : }
1418 0 : serial8250_rpm_put(up);
1419 0 : }
1420 :
1421 0 : static inline void __start_tx(struct uart_port *port)
1422 : {
1423 0 : struct uart_8250_port *up = up_to_u8250p(port);
1424 :
1425 0 : if (up->dma && !up->dma->tx_dma(up))
1426 0 : return;
1427 :
1428 0 : if (serial8250_set_THRI(up)) {
1429 0 : if (up->bugs & UART_BUG_TXEN) {
1430 0 : u16 lsr = serial_lsr_in(up);
1431 :
1432 0 : if (lsr & UART_LSR_THRE)
1433 0 : serial8250_tx_chars(up);
1434 0 : }
1435 0 : }
1436 :
1437 : /*
1438 : * Re-enable the transmitter if we disabled it.
1439 : */
1440 0 : if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1441 0 : up->acr &= ~UART_ACR_TXDIS;
1442 0 : serial_icr_write(up, UART_ACR, up->acr);
1443 0 : }
1444 0 : }
1445 :
1446 : /**
1447 : * serial8250_em485_start_tx() - generic ->rs485_start_tx() callback
1448 : * @up: uart 8250 port
1449 : * @toggle_ier: true to allow disabling receive interrupts
1450 : *
1451 : * Generic callback usable by 8250 uart drivers to start rs485 transmission.
1452 : * Assumes that setting the RTS bit in the MCR register means RTS is high.
1453 : * (Some chips use inverse semantics.) Further assumes that reception is
1454 : * stoppable by disabling the UART_IER_RDI interrupt. (Some chips set the
1455 : * UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.)
1456 : */
1457 0 : void serial8250_em485_start_tx(struct uart_8250_port *up, bool toggle_ier)
1458 : {
1459 0 : unsigned char mcr = serial8250_in_MCR(up);
1460 :
1461 0 : if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX) && toggle_ier)
1462 0 : serial8250_stop_rx(&up->port);
1463 :
1464 0 : if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1465 0 : mcr |= UART_MCR_RTS;
1466 : else
1467 0 : mcr &= ~UART_MCR_RTS;
1468 0 : serial8250_out_MCR(up, mcr);
1469 0 : }
1470 : EXPORT_SYMBOL_GPL(serial8250_em485_start_tx);
1471 :
1472 : /* Returns false, if start_tx_timer was setup to defer TX start */
1473 0 : static bool start_tx_rs485(struct uart_port *port)
1474 : {
1475 0 : struct uart_8250_port *up = up_to_u8250p(port);
1476 0 : struct uart_8250_em485 *em485 = up->em485;
1477 :
1478 : /*
1479 : * While serial8250_em485_handle_stop_tx() is a noop if
1480 : * em485->active_timer != &em485->stop_tx_timer, it might happen that
1481 : * the timer is still armed and triggers only after the current bunch of
1482 : * chars is send and em485->active_timer == &em485->stop_tx_timer again.
1483 : * So cancel the timer. There is still a theoretical race condition if
1484 : * the timer is already running and only comes around to check for
1485 : * em485->active_timer when &em485->stop_tx_timer is armed again.
1486 : */
1487 0 : if (em485->active_timer == &em485->stop_tx_timer)
1488 0 : hrtimer_try_to_cancel(&em485->stop_tx_timer);
1489 :
1490 0 : em485->active_timer = NULL;
1491 :
1492 0 : if (em485->tx_stopped) {
1493 0 : em485->tx_stopped = false;
1494 :
1495 0 : up->rs485_start_tx(up, true);
1496 :
1497 0 : if (up->port.rs485.delay_rts_before_send > 0) {
1498 0 : em485->active_timer = &em485->start_tx_timer;
1499 0 : start_hrtimer_ms(&em485->start_tx_timer,
1500 0 : up->port.rs485.delay_rts_before_send);
1501 0 : return false;
1502 : }
1503 0 : }
1504 :
1505 0 : return true;
1506 0 : }
1507 :
1508 0 : static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1509 : {
1510 0 : struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1511 : start_tx_timer);
1512 0 : struct uart_8250_port *p = em485->port;
1513 0 : unsigned long flags;
1514 :
1515 0 : uart_port_lock_irqsave(&p->port, &flags);
1516 0 : if (em485->active_timer == &em485->start_tx_timer) {
1517 0 : __start_tx(&p->port);
1518 0 : em485->active_timer = NULL;
1519 0 : }
1520 0 : uart_port_unlock_irqrestore(&p->port, flags);
1521 :
1522 0 : return HRTIMER_NORESTART;
1523 0 : }
1524 :
1525 0 : static void serial8250_start_tx(struct uart_port *port)
1526 : {
1527 0 : struct uart_8250_port *up = up_to_u8250p(port);
1528 0 : struct uart_8250_em485 *em485 = up->em485;
1529 :
1530 : /* Port locked to synchronize UART_IER access against the console. */
1531 0 : lockdep_assert_held_once(&port->lock);
1532 :
1533 0 : if (!port->x_char && kfifo_is_empty(&port->state->port.xmit_fifo))
1534 0 : return;
1535 :
1536 0 : serial8250_rpm_get_tx(up);
1537 :
1538 0 : if (em485) {
1539 0 : if ((em485->active_timer == &em485->start_tx_timer) ||
1540 0 : !start_tx_rs485(port))
1541 0 : return;
1542 0 : }
1543 0 : __start_tx(port);
1544 0 : }
1545 :
1546 0 : static void serial8250_throttle(struct uart_port *port)
1547 : {
1548 0 : port->throttle(port);
1549 0 : }
1550 :
1551 0 : static void serial8250_unthrottle(struct uart_port *port)
1552 : {
1553 0 : port->unthrottle(port);
1554 0 : }
1555 :
1556 0 : static void serial8250_disable_ms(struct uart_port *port)
1557 : {
1558 0 : struct uart_8250_port *up = up_to_u8250p(port);
1559 :
1560 : /* Port locked to synchronize UART_IER access against the console. */
1561 0 : lockdep_assert_held_once(&port->lock);
1562 :
1563 : /* no MSR capabilities */
1564 0 : if (up->bugs & UART_BUG_NOMSR)
1565 0 : return;
1566 :
1567 0 : mctrl_gpio_disable_ms_no_sync(up->gpios);
1568 :
1569 0 : up->ier &= ~UART_IER_MSI;
1570 0 : serial_port_out(port, UART_IER, up->ier);
1571 0 : }
1572 :
1573 0 : static void serial8250_enable_ms(struct uart_port *port)
1574 : {
1575 0 : struct uart_8250_port *up = up_to_u8250p(port);
1576 :
1577 : /* Port locked to synchronize UART_IER access against the console. */
1578 0 : lockdep_assert_held_once(&port->lock);
1579 :
1580 : /* no MSR capabilities */
1581 0 : if (up->bugs & UART_BUG_NOMSR)
1582 0 : return;
1583 :
1584 0 : mctrl_gpio_enable_ms(up->gpios);
1585 :
1586 0 : up->ier |= UART_IER_MSI;
1587 :
1588 0 : serial8250_rpm_get(up);
1589 0 : serial_port_out(port, UART_IER, up->ier);
1590 0 : serial8250_rpm_put(up);
1591 0 : }
1592 :
1593 0 : void serial8250_read_char(struct uart_8250_port *up, u16 lsr)
1594 : {
1595 0 : struct uart_port *port = &up->port;
1596 0 : u8 ch, flag = TTY_NORMAL;
1597 :
1598 0 : if (likely(lsr & UART_LSR_DR))
1599 0 : ch = serial_in(up, UART_RX);
1600 : else
1601 : /*
1602 : * Intel 82571 has a Serial Over Lan device that will
1603 : * set UART_LSR_BI without setting UART_LSR_DR when
1604 : * it receives a break. To avoid reading from the
1605 : * receive buffer without UART_LSR_DR bit set, we
1606 : * just force the read character to be 0
1607 : */
1608 0 : ch = 0;
1609 :
1610 0 : port->icount.rx++;
1611 :
1612 0 : lsr |= up->lsr_saved_flags;
1613 0 : up->lsr_saved_flags = 0;
1614 :
1615 0 : if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1616 0 : if (lsr & UART_LSR_BI) {
1617 0 : lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1618 0 : port->icount.brk++;
1619 : /*
1620 : * We do the SysRQ and SAK checking
1621 : * here because otherwise the break
1622 : * may get masked by ignore_status_mask
1623 : * or read_status_mask.
1624 : */
1625 0 : if (uart_handle_break(port))
1626 0 : return;
1627 0 : } else if (lsr & UART_LSR_PE)
1628 0 : port->icount.parity++;
1629 0 : else if (lsr & UART_LSR_FE)
1630 0 : port->icount.frame++;
1631 0 : if (lsr & UART_LSR_OE)
1632 0 : port->icount.overrun++;
1633 :
1634 : /*
1635 : * Mask off conditions which should be ignored.
1636 : */
1637 0 : lsr &= port->read_status_mask;
1638 :
1639 0 : if (lsr & UART_LSR_BI) {
1640 : dev_dbg(port->dev, "handling break\n");
1641 0 : flag = TTY_BREAK;
1642 0 : } else if (lsr & UART_LSR_PE)
1643 0 : flag = TTY_PARITY;
1644 0 : else if (lsr & UART_LSR_FE)
1645 0 : flag = TTY_FRAME;
1646 0 : }
1647 0 : if (uart_prepare_sysrq_char(port, ch))
1648 0 : return;
1649 :
1650 0 : uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1651 0 : }
1652 : EXPORT_SYMBOL_GPL(serial8250_read_char);
1653 :
1654 : /*
1655 : * serial8250_rx_chars - Read characters. The first LSR value must be passed in.
1656 : *
1657 : * Returns LSR bits. The caller should rely only on non-Rx related LSR bits
1658 : * (such as THRE) because the LSR value might come from an already consumed
1659 : * character.
1660 : */
1661 0 : u16 serial8250_rx_chars(struct uart_8250_port *up, u16 lsr)
1662 : {
1663 0 : struct uart_port *port = &up->port;
1664 0 : int max_count = 256;
1665 :
1666 0 : do {
1667 0 : serial8250_read_char(up, lsr);
1668 0 : if (--max_count == 0)
1669 0 : break;
1670 0 : lsr = serial_in(up, UART_LSR);
1671 0 : } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1672 :
1673 0 : tty_flip_buffer_push(&port->state->port);
1674 0 : return lsr;
1675 0 : }
1676 : EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1677 :
1678 0 : void serial8250_tx_chars(struct uart_8250_port *up)
1679 : {
1680 0 : struct uart_port *port = &up->port;
1681 0 : struct tty_port *tport = &port->state->port;
1682 0 : int count;
1683 :
1684 0 : if (port->x_char) {
1685 0 : uart_xchar_out(port, UART_TX);
1686 0 : return;
1687 : }
1688 0 : if (uart_tx_stopped(port)) {
1689 0 : serial8250_stop_tx(port);
1690 0 : return;
1691 : }
1692 0 : if (kfifo_is_empty(&tport->xmit_fifo)) {
1693 0 : __stop_tx(up);
1694 0 : return;
1695 : }
1696 :
1697 0 : count = up->tx_loadsz;
1698 0 : do {
1699 0 : unsigned char c;
1700 :
1701 0 : if (!uart_fifo_get(port, &c))
1702 0 : break;
1703 :
1704 0 : serial_out(up, UART_TX, c);
1705 0 : if (up->bugs & UART_BUG_TXRACE) {
1706 : /*
1707 : * The Aspeed BMC virtual UARTs have a bug where data
1708 : * may get stuck in the BMC's Tx FIFO from bursts of
1709 : * writes on the APB interface.
1710 : *
1711 : * Delay back-to-back writes by a read cycle to avoid
1712 : * stalling the VUART. Read a register that won't have
1713 : * side-effects and discard the result.
1714 : */
1715 0 : serial_in(up, UART_SCR);
1716 0 : }
1717 :
1718 0 : if ((up->capabilities & UART_CAP_HFIFO) &&
1719 0 : !uart_lsr_tx_empty(serial_in(up, UART_LSR)))
1720 0 : break;
1721 : /* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1722 0 : if ((up->capabilities & UART_CAP_MINI) &&
1723 0 : !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1724 0 : break;
1725 0 : } while (--count > 0);
1726 :
1727 0 : if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
1728 0 : uart_write_wakeup(port);
1729 :
1730 : /*
1731 : * With RPM enabled, we have to wait until the FIFO is empty before the
1732 : * HW can go idle. So we get here once again with empty FIFO and disable
1733 : * the interrupt and RPM in __stop_tx()
1734 : */
1735 0 : if (kfifo_is_empty(&tport->xmit_fifo) &&
1736 0 : !(up->capabilities & UART_CAP_RPM))
1737 0 : __stop_tx(up);
1738 0 : }
1739 : EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1740 :
1741 : /* Caller holds uart port lock */
1742 0 : unsigned int serial8250_modem_status(struct uart_8250_port *up)
1743 : {
1744 0 : struct uart_port *port = &up->port;
1745 0 : unsigned int status = serial_in(up, UART_MSR);
1746 :
1747 0 : status |= up->msr_saved_flags;
1748 0 : up->msr_saved_flags = 0;
1749 0 : if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1750 0 : port->state != NULL) {
1751 0 : if (status & UART_MSR_TERI)
1752 0 : port->icount.rng++;
1753 0 : if (status & UART_MSR_DDSR)
1754 0 : port->icount.dsr++;
1755 0 : if (status & UART_MSR_DDCD)
1756 0 : uart_handle_dcd_change(port, status & UART_MSR_DCD);
1757 0 : if (status & UART_MSR_DCTS)
1758 0 : uart_handle_cts_change(port, status & UART_MSR_CTS);
1759 :
1760 0 : wake_up_interruptible(&port->state->port.delta_msr_wait);
1761 0 : }
1762 :
1763 0 : return status;
1764 0 : }
1765 : EXPORT_SYMBOL_GPL(serial8250_modem_status);
1766 :
1767 0 : static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1768 : {
1769 0 : switch (iir & 0x3f) {
1770 : case UART_IIR_THRI:
1771 : /*
1772 : * Postpone DMA or not decision to IIR_RDI or IIR_RX_TIMEOUT
1773 : * because it's impossible to do an informed decision about
1774 : * that with IIR_THRI.
1775 : *
1776 : * This also fixes one known DMA Rx corruption issue where
1777 : * DR is asserted but DMA Rx only gets a corrupted zero byte
1778 : * (too early DR?).
1779 : */
1780 0 : return false;
1781 : case UART_IIR_RDI:
1782 0 : if (!up->dma->rx_running)
1783 0 : break;
1784 : fallthrough;
1785 : case UART_IIR_RLSI:
1786 : case UART_IIR_RX_TIMEOUT:
1787 0 : serial8250_rx_dma_flush(up);
1788 0 : return true;
1789 : }
1790 0 : return up->dma->rx_dma(up);
1791 0 : }
1792 :
1793 : /*
1794 : * This handles the interrupt from one port.
1795 : */
1796 0 : int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1797 : {
1798 0 : struct uart_8250_port *up = up_to_u8250p(port);
1799 0 : struct tty_port *tport = &port->state->port;
1800 0 : bool skip_rx = false;
1801 0 : unsigned long flags;
1802 0 : u16 status;
1803 :
1804 0 : if (iir & UART_IIR_NO_INT)
1805 0 : return 0;
1806 :
1807 0 : uart_port_lock_irqsave(port, &flags);
1808 :
1809 0 : status = serial_lsr_in(up);
1810 :
1811 : /*
1812 : * If port is stopped and there are no error conditions in the
1813 : * FIFO, then don't drain the FIFO, as this may lead to TTY buffer
1814 : * overflow. Not servicing, RX FIFO would trigger auto HW flow
1815 : * control when FIFO occupancy reaches preset threshold, thus
1816 : * halting RX. This only works when auto HW flow control is
1817 : * available.
1818 : */
1819 0 : if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
1820 0 : (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
1821 0 : !(up->ier & (UART_IER_RLSI | UART_IER_RDI)))
1822 0 : skip_rx = true;
1823 :
1824 0 : if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
1825 0 : struct irq_data *d;
1826 :
1827 0 : d = irq_get_irq_data(port->irq);
1828 0 : if (d && irqd_is_wakeup_set(d))
1829 0 : pm_wakeup_event(tport->tty->dev, 0);
1830 0 : if (!up->dma || handle_rx_dma(up, iir))
1831 0 : status = serial8250_rx_chars(up, status);
1832 0 : }
1833 0 : serial8250_modem_status(up);
1834 0 : if ((status & UART_LSR_THRE) && (up->ier & UART_IER_THRI)) {
1835 0 : if (!up->dma || up->dma->tx_err)
1836 0 : serial8250_tx_chars(up);
1837 0 : else if (!up->dma->tx_running)
1838 0 : __stop_tx(up);
1839 0 : }
1840 :
1841 0 : uart_unlock_and_check_sysrq_irqrestore(port, flags);
1842 :
1843 0 : return 1;
1844 0 : }
1845 : EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1846 :
1847 0 : static int serial8250_default_handle_irq(struct uart_port *port)
1848 : {
1849 0 : struct uart_8250_port *up = up_to_u8250p(port);
1850 0 : unsigned int iir;
1851 0 : int ret;
1852 :
1853 0 : serial8250_rpm_get(up);
1854 :
1855 0 : iir = serial_port_in(port, UART_IIR);
1856 0 : ret = serial8250_handle_irq(port, iir);
1857 :
1858 0 : serial8250_rpm_put(up);
1859 0 : return ret;
1860 0 : }
1861 :
1862 : /*
1863 : * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1864 : * have a programmable TX threshold that triggers the THRE interrupt in
1865 : * the IIR register. In this case, the THRE interrupt indicates the FIFO
1866 : * has space available. Load it up with tx_loadsz bytes.
1867 : */
1868 0 : static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1869 : {
1870 0 : unsigned long flags;
1871 0 : unsigned int iir = serial_port_in(port, UART_IIR);
1872 :
1873 : /* TX Threshold IRQ triggered so load up FIFO */
1874 0 : if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1875 0 : struct uart_8250_port *up = up_to_u8250p(port);
1876 :
1877 0 : uart_port_lock_irqsave(port, &flags);
1878 0 : serial8250_tx_chars(up);
1879 0 : uart_port_unlock_irqrestore(port, flags);
1880 0 : }
1881 :
1882 0 : iir = serial_port_in(port, UART_IIR);
1883 0 : return serial8250_handle_irq(port, iir);
1884 0 : }
1885 :
1886 0 : static unsigned int serial8250_tx_empty(struct uart_port *port)
1887 : {
1888 0 : struct uart_8250_port *up = up_to_u8250p(port);
1889 0 : unsigned int result = 0;
1890 0 : unsigned long flags;
1891 :
1892 0 : serial8250_rpm_get(up);
1893 :
1894 0 : uart_port_lock_irqsave(port, &flags);
1895 0 : if (!serial8250_tx_dma_running(up) && uart_lsr_tx_empty(serial_lsr_in(up)))
1896 0 : result = TIOCSER_TEMT;
1897 0 : uart_port_unlock_irqrestore(port, flags);
1898 :
1899 0 : serial8250_rpm_put(up);
1900 :
1901 0 : return result;
1902 0 : }
1903 :
1904 0 : unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1905 : {
1906 0 : struct uart_8250_port *up = up_to_u8250p(port);
1907 0 : unsigned int status;
1908 0 : unsigned int val;
1909 :
1910 0 : serial8250_rpm_get(up);
1911 0 : status = serial8250_modem_status(up);
1912 0 : serial8250_rpm_put(up);
1913 :
1914 0 : val = serial8250_MSR_to_TIOCM(status);
1915 0 : if (up->gpios)
1916 0 : return mctrl_gpio_get(up->gpios, &val);
1917 :
1918 0 : return val;
1919 0 : }
1920 : EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
1921 :
1922 0 : static unsigned int serial8250_get_mctrl(struct uart_port *port)
1923 : {
1924 0 : if (port->get_mctrl)
1925 0 : return port->get_mctrl(port);
1926 0 : return serial8250_do_get_mctrl(port);
1927 0 : }
1928 :
1929 0 : void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1930 : {
1931 0 : struct uart_8250_port *up = up_to_u8250p(port);
1932 0 : unsigned char mcr;
1933 :
1934 0 : mcr = serial8250_TIOCM_to_MCR(mctrl);
1935 :
1936 0 : mcr |= up->mcr;
1937 :
1938 0 : serial8250_out_MCR(up, mcr);
1939 0 : }
1940 : EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1941 :
1942 0 : static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1943 : {
1944 0 : if (port->rs485.flags & SER_RS485_ENABLED)
1945 0 : return;
1946 :
1947 0 : if (port->set_mctrl)
1948 0 : port->set_mctrl(port, mctrl);
1949 : else
1950 0 : serial8250_do_set_mctrl(port, mctrl);
1951 0 : }
1952 :
1953 0 : static void serial8250_break_ctl(struct uart_port *port, int break_state)
1954 : {
1955 0 : struct uart_8250_port *up = up_to_u8250p(port);
1956 0 : unsigned long flags;
1957 :
1958 0 : serial8250_rpm_get(up);
1959 0 : uart_port_lock_irqsave(port, &flags);
1960 0 : if (break_state == -1)
1961 0 : up->lcr |= UART_LCR_SBC;
1962 : else
1963 0 : up->lcr &= ~UART_LCR_SBC;
1964 0 : serial_port_out(port, UART_LCR, up->lcr);
1965 0 : uart_port_unlock_irqrestore(port, flags);
1966 0 : serial8250_rpm_put(up);
1967 0 : }
1968 :
1969 : /* Returns true if @bits were set, false on timeout */
1970 0 : static bool wait_for_lsr(struct uart_8250_port *up, int bits)
1971 : {
1972 0 : unsigned int status, tmout;
1973 :
1974 : /*
1975 : * Wait for a character to be sent. Fallback to a safe default
1976 : * timeout value if @frame_time is not available.
1977 : */
1978 0 : if (up->port.frame_time)
1979 0 : tmout = up->port.frame_time * 2 / NSEC_PER_USEC;
1980 : else
1981 0 : tmout = 10000;
1982 :
1983 0 : for (;;) {
1984 0 : status = serial_lsr_in(up);
1985 :
1986 0 : if ((status & bits) == bits)
1987 0 : break;
1988 0 : if (--tmout == 0)
1989 0 : break;
1990 0 : udelay(1);
1991 0 : touch_nmi_watchdog();
1992 : }
1993 :
1994 0 : return (tmout != 0);
1995 0 : }
1996 :
1997 : /* Wait for transmitter and holding register to empty with timeout */
1998 0 : static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1999 : {
2000 0 : unsigned int tmout;
2001 :
2002 0 : wait_for_lsr(up, bits);
2003 :
2004 : /* Wait up to 1s for flow control if necessary */
2005 0 : if (up->port.flags & UPF_CONS_FLOW) {
2006 0 : for (tmout = 1000000; tmout; tmout--) {
2007 0 : unsigned int msr = serial_in(up, UART_MSR);
2008 0 : up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2009 0 : if (msr & UART_MSR_CTS)
2010 0 : break;
2011 0 : udelay(1);
2012 0 : touch_nmi_watchdog();
2013 0 : }
2014 0 : }
2015 0 : }
2016 :
2017 : #ifdef CONFIG_CONSOLE_POLL
2018 : /*
2019 : * Console polling routines for writing and reading from the uart while
2020 : * in an interrupt or debug context.
2021 : */
2022 :
2023 : static int serial8250_get_poll_char(struct uart_port *port)
2024 : {
2025 : struct uart_8250_port *up = up_to_u8250p(port);
2026 : int status;
2027 : u16 lsr;
2028 :
2029 : serial8250_rpm_get(up);
2030 :
2031 : lsr = serial_port_in(port, UART_LSR);
2032 :
2033 : if (!(lsr & UART_LSR_DR)) {
2034 : status = NO_POLL_CHAR;
2035 : goto out;
2036 : }
2037 :
2038 : status = serial_port_in(port, UART_RX);
2039 : out:
2040 : serial8250_rpm_put(up);
2041 : return status;
2042 : }
2043 :
2044 :
2045 : static void serial8250_put_poll_char(struct uart_port *port,
2046 : unsigned char c)
2047 : {
2048 : unsigned int ier;
2049 : struct uart_8250_port *up = up_to_u8250p(port);
2050 :
2051 : /*
2052 : * Normally the port is locked to synchronize UART_IER access
2053 : * against the console. However, this function is only used by
2054 : * KDB/KGDB, where it may not be possible to acquire the port
2055 : * lock because all other CPUs are quiesced. The quiescence
2056 : * should allow safe lockless usage here.
2057 : */
2058 :
2059 : serial8250_rpm_get(up);
2060 : /*
2061 : * First save the IER then disable the interrupts
2062 : */
2063 : ier = serial_port_in(port, UART_IER);
2064 : serial8250_clear_IER(up);
2065 :
2066 : wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
2067 : /*
2068 : * Send the character out.
2069 : */
2070 : serial_port_out(port, UART_TX, c);
2071 :
2072 : /*
2073 : * Finally, wait for transmitter to become empty
2074 : * and restore the IER
2075 : */
2076 : wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
2077 : serial_port_out(port, UART_IER, ier);
2078 : serial8250_rpm_put(up);
2079 : }
2080 :
2081 : #endif /* CONFIG_CONSOLE_POLL */
2082 :
2083 0 : static void serial8250_startup_special(struct uart_port *port)
2084 : {
2085 0 : struct uart_8250_port *up = up_to_u8250p(port);
2086 0 : unsigned long flags;
2087 :
2088 0 : switch (port->type) {
2089 : case PORT_16C950:
2090 : /*
2091 : * Wake up and initialize UART
2092 : *
2093 : * Synchronize UART_IER access against the console.
2094 : */
2095 0 : uart_port_lock_irqsave(port, &flags);
2096 0 : up->acr = 0;
2097 0 : serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2098 0 : serial_port_out(port, UART_EFR, UART_EFR_ECB);
2099 0 : serial_port_out(port, UART_IER, 0);
2100 0 : serial_port_out(port, UART_LCR, 0);
2101 0 : serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2102 0 : serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2103 0 : serial_port_out(port, UART_EFR, UART_EFR_ECB);
2104 0 : serial_port_out(port, UART_LCR, 0);
2105 0 : uart_port_unlock_irqrestore(port, flags);
2106 0 : break;
2107 : case PORT_DA830:
2108 : /*
2109 : * Reset the port
2110 : *
2111 : * Synchronize UART_IER access against the console.
2112 : */
2113 0 : uart_port_lock_irqsave(port, &flags);
2114 0 : serial_port_out(port, UART_IER, 0);
2115 0 : serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2116 0 : uart_port_unlock_irqrestore(port, flags);
2117 0 : mdelay(10);
2118 :
2119 : /* Enable Tx, Rx and free run mode */
2120 0 : serial_port_out(port, UART_DA830_PWREMU_MGMT,
2121 0 : UART_DA830_PWREMU_MGMT_UTRST |
2122 0 : UART_DA830_PWREMU_MGMT_URRST |
2123 0 : UART_DA830_PWREMU_MGMT_FREE);
2124 0 : break;
2125 : case PORT_RSA:
2126 0 : rsa_enable(up);
2127 0 : break;
2128 : }
2129 0 : }
2130 :
2131 0 : static void serial8250_set_TRG_levels(struct uart_port *port)
2132 : {
2133 0 : struct uart_8250_port *up = up_to_u8250p(port);
2134 :
2135 0 : switch (port->type) {
2136 : /* For a XR16C850, we need to set the trigger levels */
2137 : case PORT_16850: {
2138 0 : u8 fctr;
2139 :
2140 0 : serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2141 :
2142 0 : fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2143 0 : fctr |= UART_FCTR_TRGD;
2144 0 : serial_port_out(port, UART_FCTR, fctr | UART_FCTR_RX);
2145 0 : serial_port_out(port, UART_TRG, UART_TRG_96);
2146 0 : serial_port_out(port, UART_FCTR, fctr | UART_FCTR_TX);
2147 0 : serial_port_out(port, UART_TRG, UART_TRG_96);
2148 :
2149 0 : serial_port_out(port, UART_LCR, 0);
2150 : break;
2151 0 : }
2152 : /* For the Altera 16550 variants, set TX threshold trigger level. */
2153 : case PORT_ALTR_16550_F32:
2154 : case PORT_ALTR_16550_F64:
2155 : case PORT_ALTR_16550_F128:
2156 0 : if (port->fifosize <= 1)
2157 0 : return;
2158 :
2159 : /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2160 0 : if (up->tx_loadsz < 2 || up->tx_loadsz > port->fifosize) {
2161 0 : dev_err(port->dev, "TX FIFO Threshold errors, skipping\n");
2162 0 : return;
2163 : }
2164 0 : serial_port_out(port, UART_ALTR_AFR, UART_ALTR_EN_TXFIFO_LW);
2165 0 : serial_port_out(port, UART_ALTR_TX_LOW, port->fifosize - up->tx_loadsz);
2166 0 : port->handle_irq = serial8250_tx_threshold_handle_irq;
2167 0 : break;
2168 : }
2169 0 : }
2170 :
2171 0 : static void serial8250_THRE_test(struct uart_port *port)
2172 : {
2173 0 : struct uart_8250_port *up = up_to_u8250p(port);
2174 0 : unsigned long flags;
2175 0 : bool iir_noint1, iir_noint2;
2176 :
2177 0 : if (!port->irq)
2178 0 : return;
2179 :
2180 0 : if (up->port.flags & UPF_NO_THRE_TEST)
2181 0 : return;
2182 :
2183 0 : if (port->irqflags & IRQF_SHARED)
2184 0 : disable_irq_nosync(port->irq);
2185 :
2186 : /*
2187 : * Test for UARTs that do not reassert THRE when the transmitter is idle and the interrupt
2188 : * has already been cleared. Real 16550s should always reassert this interrupt whenever the
2189 : * transmitter is idle and the interrupt is enabled. Delays are necessary to allow register
2190 : * changes to become visible.
2191 : *
2192 : * Synchronize UART_IER access against the console.
2193 : */
2194 0 : uart_port_lock_irqsave(port, &flags);
2195 :
2196 0 : wait_for_xmitr(up, UART_LSR_THRE);
2197 0 : serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2198 0 : udelay(1); /* allow THRE to set */
2199 0 : iir_noint1 = serial_port_in(port, UART_IIR) & UART_IIR_NO_INT;
2200 0 : serial_port_out(port, UART_IER, 0);
2201 0 : serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2202 0 : udelay(1); /* allow a working UART time to re-assert THRE */
2203 0 : iir_noint2 = serial_port_in(port, UART_IIR) & UART_IIR_NO_INT;
2204 0 : serial_port_out(port, UART_IER, 0);
2205 :
2206 0 : uart_port_unlock_irqrestore(port, flags);
2207 :
2208 0 : if (port->irqflags & IRQF_SHARED)
2209 0 : enable_irq(port->irq);
2210 :
2211 : /*
2212 : * If the interrupt is not reasserted, or we otherwise don't trust the iir, setup a timer to
2213 : * kick the UART on a regular basis.
2214 : */
2215 0 : if ((!iir_noint1 && iir_noint2) || up->port.flags & UPF_BUG_THRE)
2216 0 : up->bugs |= UART_BUG_THRE;
2217 0 : }
2218 :
2219 0 : static void serial8250_init_mctrl(struct uart_port *port)
2220 : {
2221 0 : if (port->flags & UPF_FOURPORT) {
2222 0 : if (!port->irq)
2223 0 : port->mctrl |= TIOCM_OUT1;
2224 0 : } else {
2225 : /* Most PC uarts need OUT2 raised to enable interrupts. */
2226 0 : if (port->irq)
2227 0 : port->mctrl |= TIOCM_OUT2;
2228 : }
2229 :
2230 0 : serial8250_set_mctrl(port, port->mctrl);
2231 0 : }
2232 :
2233 0 : static void serial8250_iir_txen_test(struct uart_port *port)
2234 : {
2235 0 : struct uart_8250_port *up = up_to_u8250p(port);
2236 0 : bool lsr_temt, iir_noint;
2237 :
2238 0 : if (port->quirks & UPQ_NO_TXEN_TEST)
2239 0 : return;
2240 :
2241 : /* Do a quick test to see if we receive an interrupt when we enable the TX irq. */
2242 0 : serial_port_out(port, UART_IER, UART_IER_THRI);
2243 0 : lsr_temt = serial_port_in(port, UART_LSR) & UART_LSR_TEMT;
2244 0 : iir_noint = serial_port_in(port, UART_IIR) & UART_IIR_NO_INT;
2245 0 : serial_port_out(port, UART_IER, 0);
2246 :
2247 : /*
2248 : * Serial over Lan (SoL) hack:
2249 : * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be used for Serial Over
2250 : * Lan. Those chips take a longer time than a normal serial device to signalize that a
2251 : * transmission data was queued. Due to that, the above test generally fails. One solution
2252 : * would be to delay the reading of iir. However, this is not reliable, since the timeout is
2253 : * variable. So, in case of UPQ_NO_TXEN_TEST, let's just don't test if we receive TX irq.
2254 : * This way, we'll never enable UART_BUG_TXEN.
2255 : */
2256 0 : if (lsr_temt && iir_noint) {
2257 0 : if (!(up->bugs & UART_BUG_TXEN)) {
2258 0 : up->bugs |= UART_BUG_TXEN;
2259 : dev_dbg(port->dev, "enabling bad tx status workarounds\n");
2260 0 : }
2261 0 : return;
2262 : }
2263 :
2264 : /* FIXME: why is this needed? */
2265 0 : up->bugs &= ~UART_BUG_TXEN;
2266 0 : }
2267 :
2268 0 : static void serial8250_initialize(struct uart_port *port)
2269 : {
2270 0 : unsigned long flags;
2271 :
2272 0 : uart_port_lock_irqsave(port, &flags);
2273 0 : serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2274 :
2275 0 : serial8250_init_mctrl(port);
2276 0 : serial8250_iir_txen_test(port);
2277 0 : uart_port_unlock_irqrestore(port, flags);
2278 0 : }
2279 :
2280 0 : int serial8250_do_startup(struct uart_port *port)
2281 : {
2282 0 : struct uart_8250_port *up = up_to_u8250p(port);
2283 0 : int retval;
2284 :
2285 0 : if (!port->fifosize)
2286 0 : port->fifosize = uart_config[port->type].fifo_size;
2287 0 : if (!up->tx_loadsz)
2288 0 : up->tx_loadsz = uart_config[port->type].tx_loadsz;
2289 0 : if (!up->capabilities)
2290 0 : up->capabilities = uart_config[port->type].flags;
2291 0 : up->mcr = 0;
2292 :
2293 0 : if (port->iotype != up->cur_iotype)
2294 0 : set_io_from_upio(port);
2295 :
2296 0 : serial8250_rpm_get(up);
2297 :
2298 0 : serial8250_startup_special(port);
2299 :
2300 : /*
2301 : * Clear the FIFO buffers and disable them.
2302 : * (they will be reenabled in set_termios())
2303 : */
2304 0 : serial8250_clear_fifos(up);
2305 :
2306 0 : serial8250_clear_interrupts(port);
2307 :
2308 : /*
2309 : * At this point, there's no way the LSR could still be 0xff;
2310 : * if it is, then bail out, because there's likely no UART
2311 : * here.
2312 : */
2313 0 : if (!(port->flags & UPF_BUGGY_UART) &&
2314 0 : (serial_port_in(port, UART_LSR) == 0xff)) {
2315 0 : dev_info_ratelimited(port->dev, "LSR safety check engaged!\n");
2316 0 : retval = -ENODEV;
2317 0 : goto out;
2318 : }
2319 :
2320 0 : serial8250_set_TRG_levels(port);
2321 :
2322 : /* Check if we need to have shared IRQs */
2323 0 : if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2324 0 : up->port.irqflags |= IRQF_SHARED;
2325 :
2326 0 : retval = up->ops->setup_irq(up);
2327 0 : if (retval)
2328 0 : goto out;
2329 :
2330 0 : serial8250_THRE_test(port);
2331 :
2332 0 : up->ops->setup_timer(up);
2333 :
2334 0 : serial8250_initialize(port);
2335 :
2336 : /*
2337 : * Clear the interrupt registers again for luck, and clear the
2338 : * saved flags to avoid getting false values from polling
2339 : * routines or the previous session.
2340 : */
2341 0 : serial8250_clear_interrupts(port);
2342 0 : up->lsr_saved_flags = 0;
2343 0 : up->msr_saved_flags = 0;
2344 :
2345 : /*
2346 : * Request DMA channels for both RX and TX.
2347 : */
2348 0 : if (up->dma) {
2349 0 : const char *msg = NULL;
2350 :
2351 0 : if (uart_console(port))
2352 0 : msg = "forbid DMA for kernel console";
2353 0 : else if (serial8250_request_dma(up))
2354 0 : msg = "failed to request DMA";
2355 0 : if (msg) {
2356 0 : dev_warn_ratelimited(port->dev, "%s\n", msg);
2357 0 : up->dma = NULL;
2358 0 : }
2359 0 : }
2360 :
2361 : /*
2362 : * Set the IER shadow for rx interrupts but defer actual interrupt
2363 : * enable until after the FIFOs are enabled; otherwise, an already-
2364 : * active sender can swamp the interrupt handler with "too much work".
2365 : */
2366 0 : up->ier = UART_IER_RLSI | UART_IER_RDI;
2367 :
2368 0 : if (port->flags & UPF_FOURPORT) {
2369 0 : unsigned int icp;
2370 : /*
2371 : * Enable interrupts on the AST Fourport board
2372 : */
2373 0 : icp = (port->iobase & 0xfe0) | 0x01f;
2374 0 : outb_p(0x80, icp);
2375 0 : inb_p(icp);
2376 0 : }
2377 0 : retval = 0;
2378 : out:
2379 0 : serial8250_rpm_put(up);
2380 0 : return retval;
2381 0 : }
2382 : EXPORT_SYMBOL_GPL(serial8250_do_startup);
2383 :
2384 0 : static int serial8250_startup(struct uart_port *port)
2385 : {
2386 0 : if (port->startup)
2387 0 : return port->startup(port);
2388 0 : return serial8250_do_startup(port);
2389 0 : }
2390 :
2391 0 : void serial8250_do_shutdown(struct uart_port *port)
2392 : {
2393 0 : struct uart_8250_port *up = up_to_u8250p(port);
2394 0 : unsigned long flags;
2395 :
2396 0 : serial8250_rpm_get(up);
2397 : /*
2398 : * Disable interrupts from this port
2399 : *
2400 : * Synchronize UART_IER access against the console.
2401 : */
2402 0 : uart_port_lock_irqsave(port, &flags);
2403 0 : up->ier = 0;
2404 0 : serial_port_out(port, UART_IER, 0);
2405 0 : uart_port_unlock_irqrestore(port, flags);
2406 :
2407 0 : synchronize_irq(port->irq);
2408 :
2409 0 : if (up->dma)
2410 0 : serial8250_release_dma(up);
2411 :
2412 0 : uart_port_lock_irqsave(port, &flags);
2413 0 : if (port->flags & UPF_FOURPORT) {
2414 : /* reset interrupts on the AST Fourport board */
2415 0 : inb((port->iobase & 0xfe0) | 0x1f);
2416 0 : port->mctrl |= TIOCM_OUT1;
2417 0 : } else
2418 0 : port->mctrl &= ~TIOCM_OUT2;
2419 :
2420 0 : serial8250_set_mctrl(port, port->mctrl);
2421 0 : uart_port_unlock_irqrestore(port, flags);
2422 :
2423 : /*
2424 : * Disable break condition and FIFOs
2425 : */
2426 0 : serial_port_out(port, UART_LCR,
2427 0 : serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2428 0 : serial8250_clear_fifos(up);
2429 :
2430 0 : rsa_disable(up);
2431 :
2432 : /*
2433 : * Read data port to reset things, and then unlink from
2434 : * the IRQ chain.
2435 : */
2436 0 : serial_port_in(port, UART_RX);
2437 0 : serial8250_rpm_put(up);
2438 :
2439 0 : up->ops->release_irq(up);
2440 0 : }
2441 : EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2442 :
2443 0 : static void serial8250_shutdown(struct uart_port *port)
2444 : {
2445 0 : if (port->shutdown)
2446 0 : port->shutdown(port);
2447 : else
2448 0 : serial8250_do_shutdown(port);
2449 0 : }
2450 :
2451 0 : static void serial8250_flush_buffer(struct uart_port *port)
2452 : {
2453 0 : struct uart_8250_port *up = up_to_u8250p(port);
2454 :
2455 0 : if (up->dma)
2456 0 : serial8250_tx_dma_flush(up);
2457 0 : }
2458 :
2459 0 : static unsigned int serial8250_do_get_divisor(struct uart_port *port, unsigned int baud)
2460 : {
2461 0 : upf_t magic_multiplier = port->flags & UPF_MAGIC_MULTIPLIER;
2462 0 : struct uart_8250_port *up = up_to_u8250p(port);
2463 0 : unsigned int quot;
2464 :
2465 : /*
2466 : * Handle magic divisors for baud rates above baud_base on SMSC
2467 : * Super I/O chips. We clamp custom rates from clk/6 and clk/12
2468 : * up to clk/4 (0x8001) and clk/8 (0x8002) respectively. These
2469 : * magic divisors actually reprogram the baud rate generator's
2470 : * reference clock derived from chips's 14.318MHz clock input.
2471 : *
2472 : * Documentation claims that with these magic divisors the base
2473 : * frequencies of 7.3728MHz and 3.6864MHz are used respectively
2474 : * for the extra baud rates of 460800bps and 230400bps rather
2475 : * than the usual base frequency of 1.8462MHz. However empirical
2476 : * evidence contradicts that.
2477 : *
2478 : * Instead bit 7 of the DLM register (bit 15 of the divisor) is
2479 : * effectively used as a clock prescaler selection bit for the
2480 : * base frequency of 7.3728MHz, always used. If set to 0, then
2481 : * the base frequency is divided by 4 for use by the Baud Rate
2482 : * Generator, for the usual arrangement where the value of 1 of
2483 : * the divisor produces the baud rate of 115200bps. Conversely,
2484 : * if set to 1 and high-speed operation has been enabled with the
2485 : * Serial Port Mode Register in the Device Configuration Space,
2486 : * then the base frequency is supplied directly to the Baud Rate
2487 : * Generator, so for the divisor values of 0x8001, 0x8002, 0x8003,
2488 : * 0x8004, etc. the respective baud rates produced are 460800bps,
2489 : * 230400bps, 153600bps, 115200bps, etc.
2490 : *
2491 : * In all cases only low 15 bits of the divisor are used to divide
2492 : * the baud base and therefore 32767 is the maximum divisor value
2493 : * possible, even though documentation says that the programmable
2494 : * Baud Rate Generator is capable of dividing the internal PLL
2495 : * clock by any divisor from 1 to 65535.
2496 : */
2497 0 : if (magic_multiplier && baud >= port->uartclk / 6)
2498 0 : quot = 0x8001;
2499 0 : else if (magic_multiplier && baud >= port->uartclk / 12)
2500 0 : quot = 0x8002;
2501 : else
2502 0 : quot = uart_get_divisor(port, baud);
2503 :
2504 : /*
2505 : * Oxford Semi 952 rev B workaround
2506 : */
2507 0 : if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2508 0 : quot++;
2509 :
2510 0 : return quot;
2511 0 : }
2512 :
2513 0 : static unsigned int serial8250_get_divisor(struct uart_port *port,
2514 : unsigned int baud,
2515 : unsigned int *frac)
2516 : {
2517 0 : if (port->get_divisor)
2518 0 : return port->get_divisor(port, baud, frac);
2519 :
2520 0 : return serial8250_do_get_divisor(port, baud);
2521 0 : }
2522 :
2523 0 : static unsigned char serial8250_compute_lcr(struct uart_8250_port *up, tcflag_t c_cflag)
2524 : {
2525 0 : u8 lcr = UART_LCR_WLEN(tty_get_char_size(c_cflag));
2526 :
2527 0 : if (c_cflag & CSTOPB)
2528 0 : lcr |= UART_LCR_STOP;
2529 0 : if (c_cflag & PARENB)
2530 0 : lcr |= UART_LCR_PARITY;
2531 0 : if (!(c_cflag & PARODD))
2532 0 : lcr |= UART_LCR_EPAR;
2533 0 : if (c_cflag & CMSPAR)
2534 0 : lcr |= UART_LCR_SPAR;
2535 :
2536 0 : return lcr;
2537 0 : }
2538 :
2539 0 : void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2540 : unsigned int quot)
2541 : {
2542 0 : struct uart_8250_port *up = up_to_u8250p(port);
2543 :
2544 : /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2545 0 : if (is_omap1510_8250(up)) {
2546 0 : if (baud == 115200) {
2547 0 : quot = 1;
2548 0 : serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2549 0 : } else
2550 0 : serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2551 0 : }
2552 :
2553 : /*
2554 : * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2555 : * otherwise just set DLAB
2556 : */
2557 0 : if (up->capabilities & UART_NATSEMI)
2558 0 : serial_port_out(port, UART_LCR, 0xe0);
2559 : else
2560 0 : serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2561 :
2562 0 : serial_dl_write(up, quot);
2563 0 : }
2564 : EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2565 :
2566 0 : static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2567 : unsigned int quot, unsigned int quot_frac)
2568 : {
2569 0 : if (port->set_divisor)
2570 0 : port->set_divisor(port, baud, quot, quot_frac);
2571 : else
2572 0 : serial8250_do_set_divisor(port, baud, quot);
2573 0 : }
2574 :
2575 0 : static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2576 : struct ktermios *termios,
2577 : const struct ktermios *old)
2578 : {
2579 0 : unsigned int tolerance = port->uartclk / 100;
2580 0 : unsigned int min;
2581 0 : unsigned int max;
2582 :
2583 : /*
2584 : * Handle magic divisors for baud rates above baud_base on SMSC
2585 : * Super I/O chips. Enable custom rates of clk/4 and clk/8, but
2586 : * disable divisor values beyond 32767, which are unavailable.
2587 : */
2588 0 : if (port->flags & UPF_MAGIC_MULTIPLIER) {
2589 0 : min = port->uartclk / 16 / UART_DIV_MAX >> 1;
2590 0 : max = (port->uartclk + tolerance) / 4;
2591 0 : } else {
2592 0 : min = port->uartclk / 16 / UART_DIV_MAX;
2593 0 : max = (port->uartclk + tolerance) / 16;
2594 : }
2595 :
2596 : /*
2597 : * Ask the core to calculate the divisor for us.
2598 : * Allow 1% tolerance at the upper limit so uart clks marginally
2599 : * slower than nominal still match standard baud rates without
2600 : * causing transmission errors.
2601 : */
2602 0 : return uart_get_baud_rate(port, termios, old, min, max);
2603 0 : }
2604 :
2605 : /*
2606 : * Note in order to avoid the tty port mutex deadlock don't use the next method
2607 : * within the uart port callbacks. Primarily it's supposed to be utilized to
2608 : * handle a sudden reference clock rate change.
2609 : */
2610 0 : void serial8250_update_uartclk(struct uart_port *port, unsigned int uartclk)
2611 : {
2612 0 : struct tty_port *tport = &port->state->port;
2613 0 : struct tty_struct *tty;
2614 :
2615 0 : tty = tty_port_tty_get(tport);
2616 0 : if (!tty) {
2617 0 : mutex_lock(&tport->mutex);
2618 0 : port->uartclk = uartclk;
2619 0 : mutex_unlock(&tport->mutex);
2620 0 : return;
2621 : }
2622 :
2623 0 : down_write(&tty->termios_rwsem);
2624 0 : mutex_lock(&tport->mutex);
2625 :
2626 0 : if (port->uartclk == uartclk)
2627 0 : goto out_unlock;
2628 :
2629 0 : port->uartclk = uartclk;
2630 :
2631 0 : if (!tty_port_initialized(tport))
2632 0 : goto out_unlock;
2633 :
2634 0 : serial8250_do_set_termios(port, &tty->termios, NULL);
2635 :
2636 : out_unlock:
2637 0 : mutex_unlock(&tport->mutex);
2638 0 : up_write(&tty->termios_rwsem);
2639 0 : tty_kref_put(tty);
2640 0 : }
2641 : EXPORT_SYMBOL_GPL(serial8250_update_uartclk);
2642 :
2643 0 : static void serial8250_set_mini(struct uart_port *port, struct ktermios *termios)
2644 : {
2645 0 : struct uart_8250_port *up = up_to_u8250p(port);
2646 :
2647 0 : if (!(up->capabilities & UART_CAP_MINI))
2648 0 : return;
2649 :
2650 0 : termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2651 :
2652 0 : tcflag_t csize = termios->c_cflag & CSIZE;
2653 0 : if (csize == CS5 || csize == CS6) {
2654 0 : termios->c_cflag &= ~CSIZE;
2655 0 : termios->c_cflag |= CS7;
2656 0 : }
2657 0 : }
2658 :
2659 0 : static void serial8250_set_trigger_for_slow_speed(struct uart_port *port, struct ktermios *termios,
2660 : unsigned int baud)
2661 : {
2662 0 : struct uart_8250_port *up = up_to_u8250p(port);
2663 :
2664 0 : if (!(up->capabilities & UART_CAP_FIFO))
2665 0 : return;
2666 0 : if (port->fifosize <= 1)
2667 0 : return;
2668 0 : if (baud >= 2400)
2669 0 : return;
2670 0 : if (up->dma)
2671 0 : return;
2672 :
2673 0 : up->fcr &= ~UART_FCR_TRIGGER_MASK;
2674 0 : up->fcr |= UART_FCR_TRIGGER_1;
2675 0 : }
2676 :
2677 : /*
2678 : * MCR-based auto flow control. When AFE is enabled, RTS will be deasserted when the receive FIFO
2679 : * contains more characters than the trigger, or the MCR RTS bit is cleared.
2680 : */
2681 0 : static void serial8250_set_afe(struct uart_port *port, struct ktermios *termios)
2682 : {
2683 0 : struct uart_8250_port *up = up_to_u8250p(port);
2684 :
2685 0 : if (!(up->capabilities & UART_CAP_AFE))
2686 0 : return;
2687 :
2688 0 : up->mcr &= ~UART_MCR_AFE;
2689 0 : if (termios->c_cflag & CRTSCTS)
2690 0 : up->mcr |= UART_MCR_AFE;
2691 0 : }
2692 :
2693 0 : static void serial8250_set_errors_and_ignores(struct uart_port *port, struct ktermios *termios)
2694 : {
2695 : /*
2696 : * Specify which conditions may be considered for error handling and the ignoring of
2697 : * characters. The actual ignoring of characters only occurs if the bit is set in
2698 : * @ignore_status_mask as well.
2699 : */
2700 0 : port->read_status_mask = UART_LSR_OE | UART_LSR_DR;
2701 0 : if (termios->c_iflag & INPCK)
2702 0 : port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2703 0 : if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2704 0 : port->read_status_mask |= UART_LSR_BI;
2705 :
2706 : /* Characters to ignore */
2707 0 : port->ignore_status_mask = 0;
2708 0 : if (termios->c_iflag & IGNPAR)
2709 0 : port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2710 0 : if (termios->c_iflag & IGNBRK) {
2711 0 : port->ignore_status_mask |= UART_LSR_BI;
2712 : /*
2713 : * If we're ignoring parity and break indicators, ignore overruns too (for real raw
2714 : * support).
2715 : */
2716 0 : if (termios->c_iflag & IGNPAR)
2717 0 : port->ignore_status_mask |= UART_LSR_OE;
2718 0 : }
2719 :
2720 : /* ignore all characters if CREAD is not set */
2721 0 : if ((termios->c_cflag & CREAD) == 0)
2722 0 : port->ignore_status_mask |= UART_LSR_DR;
2723 0 : }
2724 :
2725 0 : static void serial8250_set_ier(struct uart_port *port, struct ktermios *termios)
2726 : {
2727 0 : struct uart_8250_port *up = up_to_u8250p(port);
2728 :
2729 : /* CTS flow control flag and modem status interrupts */
2730 0 : up->ier &= ~UART_IER_MSI;
2731 0 : if (!(up->bugs & UART_BUG_NOMSR) && UART_ENABLE_MS(&up->port, termios->c_cflag))
2732 0 : up->ier |= UART_IER_MSI;
2733 0 : if (up->capabilities & UART_CAP_UUE)
2734 0 : up->ier |= UART_IER_UUE;
2735 0 : if (up->capabilities & UART_CAP_RTOIE)
2736 0 : up->ier |= UART_IER_RTOIE;
2737 :
2738 0 : serial_port_out(port, UART_IER, up->ier);
2739 0 : }
2740 :
2741 0 : static void serial8250_set_efr(struct uart_port *port, struct ktermios *termios)
2742 : {
2743 0 : struct uart_8250_port *up = up_to_u8250p(port);
2744 0 : u8 efr_reg = UART_EFR;
2745 0 : u8 efr = 0;
2746 :
2747 0 : if (!(up->capabilities & UART_CAP_EFR))
2748 0 : return;
2749 :
2750 : /*
2751 : * TI16C752/Startech hardware flow control. FIXME:
2752 : * - TI16C752 requires control thresholds to be set.
2753 : * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2754 : */
2755 0 : if (termios->c_cflag & CRTSCTS)
2756 0 : efr |= UART_EFR_CTS;
2757 :
2758 0 : if (port->flags & UPF_EXAR_EFR)
2759 0 : efr_reg = UART_XR_EFR;
2760 :
2761 0 : serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2762 0 : serial_port_out(port, efr_reg, efr);
2763 0 : }
2764 :
2765 0 : static void serial8250_set_fcr(struct uart_port *port, struct ktermios *termios)
2766 : {
2767 0 : struct uart_8250_port *up = up_to_u8250p(port);
2768 0 : bool is_16750 = port->type == PORT_16750;
2769 :
2770 0 : if (is_16750)
2771 0 : serial_port_out(port, UART_FCR, up->fcr);
2772 :
2773 : /*
2774 : * LCR DLAB must be reset to enable 64-byte FIFO mode. If the FCR is written without DLAB
2775 : * set, this mode will be disabled.
2776 : */
2777 0 : serial_port_out(port, UART_LCR, up->lcr);
2778 :
2779 0 : if (is_16750)
2780 0 : return;
2781 :
2782 : /* emulated UARTs (Lucent Venus 167x) need two steps */
2783 0 : if (up->fcr & UART_FCR_ENABLE_FIFO)
2784 0 : serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2785 :
2786 0 : serial_port_out(port, UART_FCR, up->fcr);
2787 0 : }
2788 :
2789 : void
2790 0 : serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2791 : const struct ktermios *old)
2792 : {
2793 0 : struct uart_8250_port *up = up_to_u8250p(port);
2794 0 : unsigned long flags;
2795 0 : unsigned int baud, quot, frac = 0;
2796 0 : u8 lcr;
2797 :
2798 0 : serial8250_set_mini(port, termios);
2799 0 : lcr = serial8250_compute_lcr(up, termios->c_cflag);
2800 0 : baud = serial8250_get_baud_rate(port, termios, old);
2801 0 : quot = serial8250_get_divisor(port, baud, &frac);
2802 :
2803 : /*
2804 : * Ok, we're now changing the port state. Do it with
2805 : * interrupts disabled.
2806 : *
2807 : * Synchronize UART_IER access against the console.
2808 : */
2809 0 : serial8250_rpm_get(up);
2810 0 : uart_port_lock_irqsave(port, &flags);
2811 :
2812 0 : up->lcr = lcr;
2813 0 : serial8250_set_trigger_for_slow_speed(port, termios, baud);
2814 0 : serial8250_set_afe(port, termios);
2815 0 : uart_update_timeout(port, termios->c_cflag, baud);
2816 0 : serial8250_set_errors_and_ignores(port, termios);
2817 0 : serial8250_set_ier(port, termios);
2818 0 : serial8250_set_efr(port, termios);
2819 0 : serial8250_set_divisor(port, baud, quot, frac);
2820 0 : serial8250_set_fcr(port, termios);
2821 0 : serial8250_set_mctrl(port, port->mctrl);
2822 :
2823 0 : uart_port_unlock_irqrestore(port, flags);
2824 0 : serial8250_rpm_put(up);
2825 :
2826 : /* Don't rewrite B0 */
2827 0 : if (tty_termios_baud_rate(termios))
2828 0 : tty_termios_encode_baud_rate(termios, baud, baud);
2829 0 : }
2830 : EXPORT_SYMBOL(serial8250_do_set_termios);
2831 :
2832 : static void
2833 0 : serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2834 : const struct ktermios *old)
2835 : {
2836 0 : if (port->set_termios)
2837 0 : port->set_termios(port, termios, old);
2838 : else
2839 0 : serial8250_do_set_termios(port, termios, old);
2840 0 : }
2841 :
2842 0 : void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2843 : {
2844 0 : if (termios->c_line == N_PPS) {
2845 0 : port->flags |= UPF_HARDPPS_CD;
2846 0 : uart_port_lock_irq(port);
2847 0 : serial8250_enable_ms(port);
2848 0 : uart_port_unlock_irq(port);
2849 0 : } else {
2850 0 : port->flags &= ~UPF_HARDPPS_CD;
2851 0 : if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2852 0 : uart_port_lock_irq(port);
2853 0 : serial8250_disable_ms(port);
2854 0 : uart_port_unlock_irq(port);
2855 0 : }
2856 : }
2857 0 : }
2858 : EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2859 :
2860 : static void
2861 0 : serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2862 : {
2863 0 : if (port->set_ldisc)
2864 0 : port->set_ldisc(port, termios);
2865 : else
2866 0 : serial8250_do_set_ldisc(port, termios);
2867 0 : }
2868 :
2869 0 : void serial8250_do_pm(struct uart_port *port, unsigned int state,
2870 : unsigned int oldstate)
2871 : {
2872 0 : struct uart_8250_port *p = up_to_u8250p(port);
2873 :
2874 0 : serial8250_set_sleep(p, state != 0);
2875 0 : }
2876 : EXPORT_SYMBOL(serial8250_do_pm);
2877 :
2878 : static void
2879 0 : serial8250_pm(struct uart_port *port, unsigned int state,
2880 : unsigned int oldstate)
2881 : {
2882 0 : if (port->pm)
2883 0 : port->pm(port, state, oldstate);
2884 : else
2885 0 : serial8250_do_pm(port, state, oldstate);
2886 0 : }
2887 :
2888 0 : static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2889 : {
2890 0 : if (pt->port.mapsize)
2891 0 : return pt->port.mapsize;
2892 0 : if (is_omap1_8250(pt))
2893 0 : return 0x16 << pt->port.regshift;
2894 :
2895 0 : return 8 << pt->port.regshift;
2896 0 : }
2897 :
2898 : /*
2899 : * Resource handling.
2900 : */
2901 0 : static int serial8250_request_std_resource(struct uart_8250_port *up)
2902 : {
2903 0 : unsigned int size = serial8250_port_size(up);
2904 0 : struct uart_port *port = &up->port;
2905 :
2906 0 : switch (port->iotype) {
2907 : case UPIO_AU:
2908 : case UPIO_TSI:
2909 : case UPIO_MEM32:
2910 : case UPIO_MEM32BE:
2911 : case UPIO_MEM16:
2912 : case UPIO_MEM:
2913 0 : if (!port->mapbase)
2914 0 : return -EINVAL;
2915 :
2916 0 : if (!request_mem_region(port->mapbase, size, "serial"))
2917 0 : return -EBUSY;
2918 :
2919 0 : if (port->flags & UPF_IOREMAP) {
2920 0 : port->membase = ioremap(port->mapbase, size);
2921 0 : if (!port->membase) {
2922 0 : release_mem_region(port->mapbase, size);
2923 0 : return -ENOMEM;
2924 : }
2925 0 : }
2926 0 : return 0;
2927 : case UPIO_HUB6:
2928 : case UPIO_PORT:
2929 0 : if (!request_region(port->iobase, size, "serial"))
2930 0 : return -EBUSY;
2931 0 : return 0;
2932 : case UPIO_UNKNOWN:
2933 0 : break;
2934 : }
2935 :
2936 0 : return 0;
2937 0 : }
2938 :
2939 0 : static void serial8250_release_std_resource(struct uart_8250_port *up)
2940 : {
2941 0 : unsigned int size = serial8250_port_size(up);
2942 0 : struct uart_port *port = &up->port;
2943 :
2944 0 : switch (port->iotype) {
2945 : case UPIO_AU:
2946 : case UPIO_TSI:
2947 : case UPIO_MEM32:
2948 : case UPIO_MEM32BE:
2949 : case UPIO_MEM16:
2950 : case UPIO_MEM:
2951 0 : if (!port->mapbase)
2952 0 : break;
2953 :
2954 0 : if (port->flags & UPF_IOREMAP) {
2955 0 : iounmap(port->membase);
2956 0 : port->membase = NULL;
2957 0 : }
2958 :
2959 0 : release_mem_region(port->mapbase, size);
2960 0 : break;
2961 :
2962 : case UPIO_HUB6:
2963 : case UPIO_PORT:
2964 0 : release_region(port->iobase, size);
2965 0 : break;
2966 : case UPIO_UNKNOWN:
2967 0 : break;
2968 : }
2969 0 : }
2970 :
2971 0 : static void serial8250_release_port(struct uart_port *port)
2972 : {
2973 0 : struct uart_8250_port *up = up_to_u8250p(port);
2974 :
2975 0 : serial8250_release_std_resource(up);
2976 0 : }
2977 :
2978 0 : static int serial8250_request_port(struct uart_port *port)
2979 : {
2980 0 : struct uart_8250_port *up = up_to_u8250p(port);
2981 :
2982 0 : return serial8250_request_std_resource(up);
2983 0 : }
2984 :
2985 0 : static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2986 : {
2987 0 : const struct serial8250_config *conf_type = &uart_config[up->port.type];
2988 0 : unsigned char bytes;
2989 :
2990 0 : bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2991 :
2992 0 : return bytes ? bytes : -EOPNOTSUPP;
2993 0 : }
2994 :
2995 0 : static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2996 : {
2997 0 : const struct serial8250_config *conf_type = &uart_config[up->port.type];
2998 0 : int i;
2999 :
3000 0 : if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
3001 0 : return -EOPNOTSUPP;
3002 :
3003 0 : for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
3004 0 : if (bytes < conf_type->rxtrig_bytes[i])
3005 : /* Use the nearest lower value */
3006 0 : return (--i) << UART_FCR_R_TRIG_SHIFT;
3007 0 : }
3008 :
3009 0 : return UART_FCR_R_TRIG_11;
3010 0 : }
3011 :
3012 0 : static int do_get_rxtrig(struct tty_port *port)
3013 : {
3014 0 : struct uart_state *state = container_of(port, struct uart_state, port);
3015 0 : struct uart_port *uport = state->uart_port;
3016 0 : struct uart_8250_port *up = up_to_u8250p(uport);
3017 :
3018 0 : if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3019 0 : return -EINVAL;
3020 :
3021 0 : return fcr_get_rxtrig_bytes(up);
3022 0 : }
3023 :
3024 0 : static int do_serial8250_get_rxtrig(struct tty_port *port)
3025 : {
3026 0 : int rxtrig_bytes;
3027 :
3028 0 : mutex_lock(&port->mutex);
3029 0 : rxtrig_bytes = do_get_rxtrig(port);
3030 0 : mutex_unlock(&port->mutex);
3031 :
3032 0 : return rxtrig_bytes;
3033 0 : }
3034 :
3035 0 : static ssize_t rx_trig_bytes_show(struct device *dev,
3036 : struct device_attribute *attr, char *buf)
3037 : {
3038 0 : struct tty_port *port = dev_get_drvdata(dev);
3039 0 : int rxtrig_bytes;
3040 :
3041 0 : rxtrig_bytes = do_serial8250_get_rxtrig(port);
3042 0 : if (rxtrig_bytes < 0)
3043 0 : return rxtrig_bytes;
3044 :
3045 0 : return sysfs_emit(buf, "%d\n", rxtrig_bytes);
3046 0 : }
3047 :
3048 0 : static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
3049 : {
3050 0 : struct uart_state *state = container_of(port, struct uart_state, port);
3051 0 : struct uart_port *uport = state->uart_port;
3052 0 : struct uart_8250_port *up = up_to_u8250p(uport);
3053 0 : int rxtrig;
3054 :
3055 0 : if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3056 0 : return -EINVAL;
3057 :
3058 0 : rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3059 0 : if (rxtrig < 0)
3060 0 : return rxtrig;
3061 :
3062 0 : serial8250_clear_fifos(up);
3063 0 : up->fcr &= ~UART_FCR_TRIGGER_MASK;
3064 0 : up->fcr |= (unsigned char)rxtrig;
3065 0 : serial_out(up, UART_FCR, up->fcr);
3066 0 : return 0;
3067 0 : }
3068 :
3069 0 : static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3070 : {
3071 0 : int ret;
3072 :
3073 0 : mutex_lock(&port->mutex);
3074 0 : ret = do_set_rxtrig(port, bytes);
3075 0 : mutex_unlock(&port->mutex);
3076 :
3077 0 : return ret;
3078 0 : }
3079 :
3080 0 : static ssize_t rx_trig_bytes_store(struct device *dev,
3081 : struct device_attribute *attr, const char *buf, size_t count)
3082 : {
3083 0 : struct tty_port *port = dev_get_drvdata(dev);
3084 0 : unsigned char bytes;
3085 0 : int ret;
3086 :
3087 0 : if (!count)
3088 0 : return -EINVAL;
3089 :
3090 0 : ret = kstrtou8(buf, 10, &bytes);
3091 0 : if (ret < 0)
3092 0 : return ret;
3093 :
3094 0 : ret = do_serial8250_set_rxtrig(port, bytes);
3095 0 : if (ret < 0)
3096 0 : return ret;
3097 :
3098 0 : return count;
3099 0 : }
3100 :
3101 : static DEVICE_ATTR_RW(rx_trig_bytes);
3102 :
3103 : static struct attribute *serial8250_dev_attrs[] = {
3104 : &dev_attr_rx_trig_bytes.attr,
3105 : NULL
3106 : };
3107 :
3108 : static struct attribute_group serial8250_dev_attr_group = {
3109 : .attrs = serial8250_dev_attrs,
3110 : };
3111 :
3112 0 : static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3113 : {
3114 0 : const struct serial8250_config *conf_type = &uart_config[up->port.type];
3115 :
3116 0 : if (conf_type->rxtrig_bytes[0])
3117 0 : up->port.attr_group = &serial8250_dev_attr_group;
3118 0 : }
3119 :
3120 0 : static void serial8250_config_port(struct uart_port *port, int flags)
3121 : {
3122 0 : struct uart_8250_port *up = up_to_u8250p(port);
3123 0 : int ret;
3124 :
3125 : /*
3126 : * Find the region that we can probe for. This in turn
3127 : * tells us whether we can probe for the type of port.
3128 : */
3129 0 : ret = serial8250_request_std_resource(up);
3130 0 : if (ret < 0)
3131 0 : return;
3132 :
3133 0 : if (port->iotype != up->cur_iotype)
3134 0 : set_io_from_upio(port);
3135 :
3136 0 : if (flags & UART_CONFIG_TYPE)
3137 0 : autoconfig(up);
3138 :
3139 : /* HW bugs may trigger IRQ while IIR == NO_INT */
3140 0 : if (port->type == PORT_TEGRA)
3141 0 : up->bugs |= UART_BUG_NOMSR;
3142 :
3143 0 : if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3144 0 : autoconfig_irq(up);
3145 :
3146 0 : if (port->type == PORT_UNKNOWN)
3147 0 : serial8250_release_std_resource(up);
3148 :
3149 0 : register_dev_spec_attr_grp(up);
3150 0 : up->fcr = uart_config[up->port.type].fcr;
3151 0 : }
3152 :
3153 : static int
3154 0 : serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3155 : {
3156 0 : if (ser->irq >= irq_get_nr_irqs() || ser->irq < 0 ||
3157 0 : ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3158 0 : ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3159 0 : ser->type == PORT_STARTECH)
3160 0 : return -EINVAL;
3161 0 : return 0;
3162 0 : }
3163 :
3164 0 : static const char *serial8250_type(struct uart_port *port)
3165 : {
3166 0 : int type = port->type;
3167 :
3168 0 : if (type >= ARRAY_SIZE(uart_config))
3169 0 : type = 0;
3170 0 : return uart_config[type].name;
3171 0 : }
3172 :
3173 : static const struct uart_ops serial8250_pops = {
3174 : .tx_empty = serial8250_tx_empty,
3175 : .set_mctrl = serial8250_set_mctrl,
3176 : .get_mctrl = serial8250_get_mctrl,
3177 : .stop_tx = serial8250_stop_tx,
3178 : .start_tx = serial8250_start_tx,
3179 : .throttle = serial8250_throttle,
3180 : .unthrottle = serial8250_unthrottle,
3181 : .stop_rx = serial8250_stop_rx,
3182 : .enable_ms = serial8250_enable_ms,
3183 : .break_ctl = serial8250_break_ctl,
3184 : .startup = serial8250_startup,
3185 : .shutdown = serial8250_shutdown,
3186 : .flush_buffer = serial8250_flush_buffer,
3187 : .set_termios = serial8250_set_termios,
3188 : .set_ldisc = serial8250_set_ldisc,
3189 : .pm = serial8250_pm,
3190 : .type = serial8250_type,
3191 : .release_port = serial8250_release_port,
3192 : .request_port = serial8250_request_port,
3193 : .config_port = serial8250_config_port,
3194 : .verify_port = serial8250_verify_port,
3195 : #ifdef CONFIG_CONSOLE_POLL
3196 : .poll_get_char = serial8250_get_poll_char,
3197 : .poll_put_char = serial8250_put_poll_char,
3198 : #endif
3199 : };
3200 :
3201 0 : void serial8250_init_port(struct uart_8250_port *up)
3202 : {
3203 0 : struct uart_port *port = &up->port;
3204 :
3205 0 : spin_lock_init(&port->lock);
3206 0 : port->ctrl_id = 0;
3207 0 : port->pm = NULL;
3208 0 : port->ops = &serial8250_pops;
3209 0 : port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
3210 :
3211 0 : up->cur_iotype = UPIO_UNKNOWN;
3212 0 : }
3213 : EXPORT_SYMBOL_GPL(serial8250_init_port);
3214 :
3215 0 : void serial8250_set_defaults(struct uart_8250_port *up)
3216 : {
3217 0 : struct uart_port *port = &up->port;
3218 :
3219 0 : if (up->port.flags & UPF_FIXED_TYPE) {
3220 0 : unsigned int type = up->port.type;
3221 :
3222 0 : if (!up->port.fifosize)
3223 0 : up->port.fifosize = uart_config[type].fifo_size;
3224 0 : if (!up->tx_loadsz)
3225 0 : up->tx_loadsz = uart_config[type].tx_loadsz;
3226 0 : if (!up->capabilities)
3227 0 : up->capabilities = uart_config[type].flags;
3228 0 : }
3229 :
3230 0 : set_io_from_upio(port);
3231 :
3232 : /* default dma handlers */
3233 0 : if (up->dma) {
3234 0 : if (!up->dma->tx_dma)
3235 0 : up->dma->tx_dma = serial8250_tx_dma;
3236 0 : if (!up->dma->rx_dma)
3237 0 : up->dma->rx_dma = serial8250_rx_dma;
3238 0 : }
3239 0 : }
3240 : EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3241 :
3242 : #ifdef CONFIG_SERIAL_8250_CONSOLE
3243 :
3244 0 : static void serial8250_console_putchar(struct uart_port *port, unsigned char ch)
3245 : {
3246 0 : serial_port_out(port, UART_TX, ch);
3247 0 : }
3248 :
3249 0 : static void serial8250_console_wait_putchar(struct uart_port *port, unsigned char ch)
3250 : {
3251 0 : struct uart_8250_port *up = up_to_u8250p(port);
3252 :
3253 0 : wait_for_xmitr(up, UART_LSR_THRE);
3254 0 : serial8250_console_putchar(port, ch);
3255 0 : }
3256 :
3257 : /*
3258 : * Restore serial console when h/w power-off detected
3259 : */
3260 0 : static void serial8250_console_restore(struct uart_8250_port *up)
3261 : {
3262 0 : struct uart_port *port = &up->port;
3263 0 : struct ktermios termios;
3264 0 : unsigned int baud, quot, frac = 0;
3265 :
3266 0 : termios.c_cflag = port->cons->cflag;
3267 0 : termios.c_ispeed = port->cons->ispeed;
3268 0 : termios.c_ospeed = port->cons->ospeed;
3269 0 : if (port->state->port.tty && termios.c_cflag == 0) {
3270 0 : termios.c_cflag = port->state->port.tty->termios.c_cflag;
3271 0 : termios.c_ispeed = port->state->port.tty->termios.c_ispeed;
3272 0 : termios.c_ospeed = port->state->port.tty->termios.c_ospeed;
3273 0 : }
3274 :
3275 0 : baud = serial8250_get_baud_rate(port, &termios, NULL);
3276 0 : quot = serial8250_get_divisor(port, baud, &frac);
3277 :
3278 0 : serial8250_set_divisor(port, baud, quot, frac);
3279 0 : serial_port_out(port, UART_LCR, up->lcr);
3280 0 : serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS);
3281 0 : }
3282 :
3283 0 : static void fifo_wait_for_lsr(struct uart_8250_port *up, unsigned int count)
3284 : {
3285 0 : unsigned int i;
3286 :
3287 0 : for (i = 0; i < count; i++) {
3288 0 : if (wait_for_lsr(up, UART_LSR_THRE))
3289 0 : return;
3290 0 : }
3291 0 : }
3292 :
3293 : /*
3294 : * Print a string to the serial port using the device FIFO
3295 : *
3296 : * It sends fifosize bytes and then waits for the fifo
3297 : * to get empty.
3298 : */
3299 0 : static void serial8250_console_fifo_write(struct uart_8250_port *up,
3300 : const char *s, unsigned int count)
3301 : {
3302 0 : const char *end = s + count;
3303 0 : unsigned int fifosize = up->tx_loadsz;
3304 0 : struct uart_port *port = &up->port;
3305 0 : unsigned int tx_count = 0;
3306 0 : bool cr_sent = false;
3307 0 : unsigned int i;
3308 :
3309 0 : while (s != end) {
3310 : /* Allow timeout for each byte of a possibly full FIFO */
3311 0 : fifo_wait_for_lsr(up, fifosize);
3312 :
3313 0 : for (i = 0; i < fifosize && s != end; ++i) {
3314 0 : if (*s == '\n' && !cr_sent) {
3315 0 : serial8250_console_putchar(port, '\r');
3316 0 : cr_sent = true;
3317 0 : } else {
3318 0 : serial8250_console_putchar(port, *s++);
3319 0 : cr_sent = false;
3320 : }
3321 0 : }
3322 0 : tx_count = i;
3323 : }
3324 :
3325 : /*
3326 : * Allow timeout for each byte written since the caller will only wait
3327 : * for UART_LSR_BOTH_EMPTY using the timeout of a single character
3328 : */
3329 0 : fifo_wait_for_lsr(up, tx_count);
3330 0 : }
3331 :
3332 : /*
3333 : * Print a string to the serial port trying not to disturb
3334 : * any possible real use of the port...
3335 : *
3336 : * The console_lock must be held when we get here.
3337 : *
3338 : * Doing runtime PM is really a bad idea for the kernel console.
3339 : * Thus, we assume the function is called when device is powered up.
3340 : */
3341 0 : void serial8250_console_write(struct uart_8250_port *up, const char *s,
3342 : unsigned int count)
3343 : {
3344 0 : struct uart_8250_em485 *em485 = up->em485;
3345 0 : struct uart_port *port = &up->port;
3346 0 : unsigned long flags;
3347 0 : unsigned int ier, use_fifo;
3348 0 : int locked = 1;
3349 :
3350 0 : touch_nmi_watchdog();
3351 :
3352 0 : if (oops_in_progress)
3353 0 : locked = uart_port_trylock_irqsave(port, &flags);
3354 : else
3355 0 : uart_port_lock_irqsave(port, &flags);
3356 :
3357 : /*
3358 : * First save the IER then disable the interrupts
3359 : */
3360 0 : ier = serial_port_in(port, UART_IER);
3361 0 : serial8250_clear_IER(up);
3362 :
3363 : /* check scratch reg to see if port powered off during system sleep */
3364 0 : if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3365 0 : serial8250_console_restore(up);
3366 0 : up->canary = 0;
3367 0 : }
3368 :
3369 0 : if (em485) {
3370 0 : if (em485->tx_stopped)
3371 0 : up->rs485_start_tx(up, false);
3372 0 : mdelay(port->rs485.delay_rts_before_send);
3373 0 : }
3374 :
3375 0 : use_fifo = (up->capabilities & UART_CAP_FIFO) &&
3376 : /*
3377 : * BCM283x requires to check the fifo
3378 : * after each byte.
3379 : */
3380 0 : !(up->capabilities & UART_CAP_MINI) &&
3381 : /*
3382 : * tx_loadsz contains the transmit fifo size
3383 : */
3384 0 : up->tx_loadsz > 1 &&
3385 0 : (up->fcr & UART_FCR_ENABLE_FIFO) &&
3386 0 : port->state &&
3387 0 : test_bit(TTY_PORT_INITIALIZED, &port->state->port.iflags) &&
3388 : /*
3389 : * After we put a data in the fifo, the controller will send
3390 : * it regardless of the CTS state. Therefore, only use fifo
3391 : * if we don't use control flow.
3392 : */
3393 0 : !(up->port.flags & UPF_CONS_FLOW);
3394 :
3395 0 : if (likely(use_fifo))
3396 0 : serial8250_console_fifo_write(up, s, count);
3397 : else
3398 0 : uart_console_write(port, s, count, serial8250_console_wait_putchar);
3399 :
3400 : /*
3401 : * Finally, wait for transmitter to become empty
3402 : * and restore the IER
3403 : */
3404 0 : wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
3405 :
3406 0 : if (em485) {
3407 0 : mdelay(port->rs485.delay_rts_after_send);
3408 0 : if (em485->tx_stopped)
3409 0 : up->rs485_stop_tx(up, false);
3410 0 : }
3411 :
3412 0 : serial_port_out(port, UART_IER, ier);
3413 :
3414 : /*
3415 : * The receive handling will happen properly because the
3416 : * receive ready bit will still be set; it is not cleared
3417 : * on read. However, modem control will not, we must
3418 : * call it if we have saved something in the saved flags
3419 : * while processing with interrupts off.
3420 : */
3421 0 : if (up->msr_saved_flags)
3422 0 : serial8250_modem_status(up);
3423 :
3424 0 : if (locked)
3425 0 : uart_port_unlock_irqrestore(port, flags);
3426 0 : }
3427 :
3428 0 : static unsigned int probe_baud(struct uart_port *port)
3429 : {
3430 0 : unsigned char lcr, dll, dlm;
3431 0 : unsigned int quot;
3432 :
3433 0 : lcr = serial_port_in(port, UART_LCR);
3434 0 : serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3435 0 : dll = serial_port_in(port, UART_DLL);
3436 0 : dlm = serial_port_in(port, UART_DLM);
3437 0 : serial_port_out(port, UART_LCR, lcr);
3438 :
3439 0 : quot = (dlm << 8) | dll;
3440 0 : return (port->uartclk / 16) / quot;
3441 0 : }
3442 :
3443 0 : int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3444 : {
3445 0 : int baud = 9600;
3446 0 : int bits = 8;
3447 0 : int parity = 'n';
3448 0 : int flow = 'n';
3449 0 : int ret;
3450 :
3451 0 : if (!port->iobase && !port->membase)
3452 0 : return -ENODEV;
3453 :
3454 0 : if (options)
3455 0 : uart_parse_options(options, &baud, &parity, &bits, &flow);
3456 0 : else if (probe)
3457 0 : baud = probe_baud(port);
3458 :
3459 0 : ret = uart_set_options(port, port->cons, baud, parity, bits, flow);
3460 0 : if (ret)
3461 0 : return ret;
3462 :
3463 0 : if (port->dev)
3464 0 : pm_runtime_get_sync(port->dev);
3465 :
3466 0 : return 0;
3467 0 : }
3468 :
3469 0 : int serial8250_console_exit(struct uart_port *port)
3470 : {
3471 0 : if (port->dev)
3472 0 : pm_runtime_put_sync(port->dev);
3473 :
3474 0 : return 0;
3475 : }
3476 :
3477 : #endif /* CONFIG_SERIAL_8250_CONSOLE */
3478 :
3479 : MODULE_DESCRIPTION("Base port operations for 8250/16550-type serial ports");
3480 : MODULE_LICENSE("GPL");
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